Controlling performance states of processing engines of a processor

Patent metadata

Field	Value
Publication number	US-2016349828-A1
Application number	US-201514722518-A
Country	US
Kind code	A1
Filing date	May 27, 2015
Priority date	May 27, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . A processor comprising:
a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the plurality of processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines.

2 . The processor of claim 1 , wherein the first logic is to increase the window length when a sum of the estimated activity level and a threshold value is less than the average number of active processing engines.

3 . The processor of claim 2 , wherein the increased window length is to cause the performance state control logic to control the performance state of the at least one of the plurality of processing engines at a reduced rate.

4 . The processor of claim 1 , wherein the first logic is to only adjust the at least one activity level threshold based at least in part on the comparison.

5 . The processor of claim 4 , wherein the first logic is to adjust a first activity level threshold and a second activity level threshold in a first direction, to cause the performance state control logic to increase the performance state of the at least one processing engine at a reduced rate.

6 . The processor of claim 5 , wherein the power state control logic is to increase the performance state of the at least one processing engine when an average core utilization value exceeds the first activity level threshold.

7 . The processor of claim 1 , wherein the first logic is to determine the estimated activity level according to a value stored in an entry of a configuration storage, the entry to be accessed based at least in part on a maximum active state residency of one of the plurality of processing engines.

8 . The processor of claim 1 , wherein the estimated activity level is less than the average number of active processing engines when the first processing engine and the second processing engine execute a parallel workload.

9 . The processor of claim 1 , wherein the estimated activity level is greater than the average number of active processing engines when the first processing engine and the second processing engine execute independent workloads.

10 . The processor of claim 1 , wherein the processor further comprises:
a first counter to maintain a first count of clock cycles when the plurality of processing engines are active; and a second counter to maintain a second count of clock cycles when at least one of the plurality of processing engines is active.

11 . The processor of claim 10 , wherein the first logic is to determine the average number of active cores based at least in part on the first count and the second count.

12 . The processor of claim 1 , wherein the power state control logic is to receive a request from a user for a first performance state for the processor, and prevent operation of the processor at the first performance state based on the comparison of the estimated activity level and the average number of active processing engines.

13 . The processor of claim 1 , wherein the power state control logic is to increase the performance state of the at least one processing engine when the processor is to execute a user interactive workload and to prevent the performance state increase when the processor is to execute a non-user interactive workload.

14 . A machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
measuring an activity overlap between a first processing engine and a second processing engine of a processor during an evaluation interval; estimating an expected activity overlap between the first processing engine and the second processing engine; and responsive to the measured activity overlap exceeding the expected activity overlap, enabling a performance state of at least one of the first processing engine and the second processing engine to be increased.

15 . The machine-readable medium of claim 14 , wherein the method further comprises responsive to the measured activity overlap being less than the expected activity overlap, preventing the performance state of the at least one of the first processing engine and the second processing engine from being increased.

16 . The machine-readable medium of claim 14 , wherein the method further comprises measuring the activity overlap based at least in part on a count value of a counter, wherein the counter is updated when the first processing engine and the second processing engine are concurrently in an active state.

17 . The machine-readable medium of claim 16 , wherein estimating the expected activity overlap comprises calculating the expected activity overlap based on a first utilization value of the first processing engine, a second utilization value of the second processing engine, and a duration of the evaluation interval.

18 . The machine-readable medium of claim 14 , wherein the method further comprises preventing the first processing engine from operating at a higher performance state if the second processing engine is to be in an active state after the first processing engine completes a pending workload.

19 . A system comprising:
a processor including a first domain having a plurality of cores, a second domain having at least one graphics engine, and a power controller to control a performance state of the first domain based at least on part on a correlation of execution of a first workload on the first domain and execution of a second workload on the second domain; and a dynamic random access memory (DRAM) coupled to the processor.

20 . The system of claim 19 , wherein the power controller is further to determine an average number of active processing engines of the first domain and the second domain over a first window, an estimated activity level of the processor for the first window, and adjust a window length at which the power controller is to control the performance state, based at least in part on a comparison of the estimated activity level and the average number of active processing engines.

21 . The system of claim 20 , wherein the power controller is to increase the window length when a sum of the estimated activity level and a threshold value is less than the average number of active processing engines.

22 . The system of claim 20 , wherein the power controller is to receive a request from a user for a first performance state for the processor, and prevent operation of the processor at the first performance state based on the comparison of the estimated activity level and the average number of active processing engines.

23 . The system of claim 19 , wherein the processor further comprises:
a first counter to maintain a first count of clock cycles when the plurality of cores are active; and a second counter to maintain a second count of clock cycles when at least one of the plurality of co

Assignees

• Intel Corp

Inventors

• Weissmann Eliezer
• Rotem Efraim
• Abu Salah Hisham
• Aizik Yoni
• Rajwan Doron
• Rosenzweig Nir
• Leibovich Gal
• Sabin Yevgeni
• Levy Shay

Classifications

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title