Semiconductor device and method

US11848288B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11848288-B2
Application numberUS-202117385222-A
CountryUS
Kind codeB2
Filing dateJul 26, 2021
Priority dateSep 29, 2017
Publication dateDec 19, 2023
Grant dateDec 19, 2023

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.

First claim

Opening claim text (preview).

What is claimed is: 1. A device comprising: a first dielectric layer; a conductive shield on the first dielectric layer; a second dielectric layer on the conductive shield and the first dielectric layer, a first portion of the second dielectric layer extending along an edge of the conductive shield, a second portion of the second dielectric layer extending through a center of the conductive shield, a third portion of the second dielectric layer extending through a channel of the conductive shield, the third portion connecting the first portion to the second portion; an integrated circuit die on a surface of the second dielectric layer, the integrated circuit die laterally disposed outside the edge of the conductive shield, the integrated circuit die comprising a die connector; an encapsulant around the integrated circuit die; and a coil extending through the encapsulant such that the coil extends from a bottom surface of the encapsulant to a top surface of the encapsulant, the coil laterally disposed inside the edge of the conductive shield, the coil comprising conductive segments on the surface of the second dielectric layer, the conductive segments winding around the center of the conductive shield at continuously increasing distances from the center of the conductive shield, wherein the top surface of the encapsulant is substantially coplanar with a top surface of the die connector and with top surfaces of the conductive segments, wherein the top surfaces of the conductive segments, the top surface of the die connector, and the top surface of the encapsulant face away from the second dielectric layer. 2. The device of claim 1 further comprising: a dummy semiconductor structure in the center of the coil, the encapsulant disposed around the dummy semiconductor structure. 3. The device of claim 1 , wherein the coil emanates from a first end and terminates at a second end, the device further comprising: a redistribution structure on the encapsulant, the redistribution structure comprising metallization patterns, the metallization patterns connecting the first end and the second end of the coil to the integrated circuit die. 4. The device of claim 3 , wherein the redistribution structure is disposed on the top surfaces of the conductive segments, the top surface of the integrated circuit die, and the top surface of the encapsulant. 5. The device of claim 3 further comprising: a ferric structure adhered to the redistribution structure, the ferric structure laterally disposed inside the edge of the conductive shield. 6. The device of claim 3 further comprising: a passive device connected to the metallization patterns of the redistribution structure, the passive device laterally disposed outside the edge of the conductive shield. 7. A device comprising: a first dielectric layer; a metal shield on the first dielectric layer, the metal shield having a center region, an outer periphery, and a channel region, the channel region extending between the center region and the outer periphery; a second dielectric layer on the metal shield and the first dielectric layer, the second dielectric layer extending through the center region and the channel region of the metal shield; an encapsulant on a surface of the second dielectric layer; a metal coil extending completely through the encapsulant, a center of the metal coil aligned with the center region of the metal shield, the metal coil comprising through vias on the surface of the second dielectric layer, the through vias winding around the center of the metal coil at continuously increasing distances from the center of the metal coil; and an integrated circuit die in the encapsulant, the integrated circuit die laterally disposed outside of the metal coil, the integrated circuit die comprising a die connector, the die connector facing away from the second dielectric layer, wherein a top surface of the encapsulant is substantially coplanar with a top surface of the die connector and with top surfaces of the through vias. 8. The device of claim 7 further comprising: a dummy semiconductor structure in the center of the metal coil, the dummy semiconductor structure disposed in the encapsulant. 9. The device of claim 7 , wherein the metal coil has a first end and a second end, the device further comprising: a redistribution structure on the encapsulant, the redistribution structure comprising metallization patterns, the metallization patterns connected to the first end of the metal coil, the second end of the metal coil, and the integrated circuit die. 10. The device of claim 9 further comprising: a ferric structure on the redistribution structure, edges of the ferric structure being co-terminus with edges of the metal coil; and a passive device on the redistribution structure, the passive device connected to the integrated circuit die, the passive device being different from the ferric structure. 11. The device of claim 7 , wherein the metal coil has a first end and a second end, the first end disposed closer to the center region of the metal shield than to the outer periphery of the metal shield, the second end disposed closer to the outer periphery of the metal shield than to the center region of the metal shield. 12. A device comprising: a back-side shielding structure comprising a conductive shield, the conductive shield having a slot extending between a center and an edge of the conductive shield; a conductive coil comprising through vias on a surface of the back-side shielding structure, the through vias winding around a center of the conductive coil at continuously increasing distances from the center of the conductive coil, the center of the conductive coil aligned with the center of the conductive shield; a semiconductor structure in the center of the conductive coil, the semiconductor structure disposed on the surface of the back-side shielding structure; an integrated circuit die on the surface of the back-side shielding structure; and an encapsulant around the integrated circuit die, the semiconductor structure, and the conductive coil, the through vias of the conductive coil each extending from a bottom surface of the encapsulant to a top surface of the encapsulant, the bottom surface of the encapsulant facing towards the back-side shielding structure, the top surface of the encapsulant facing away from the back-side shielding structure, wherein the top surface of the encapsulant is substantially coplanar with a top surface of the integrated circuit die, a top surface of the semiconductor structure, and top surfaces of the through vias. 13. The device of claim 12 further comprising: a passive device outside of the conductive coil, the passive device connected to the integrated circuit die. 14. The device of claim 12 , wherein the conductive coil has a first end and a second end, the device further comprising: a front-side redistribution structure on the encapsulant, the front-side redistribution structure comprising metallization patterns, the metallization patterns connecting the first end and the second end of the conductive coil to the integrated circuit die. 15. The device of claim 14 further comprising: a ferric structure adhered to the front-side redistribution structure, the ferric structure overlapping the conductive coil. 16. The device of claim 12 , wherein the conductive coil has a first end and a second end, the first end disposed proximate the center of the conductive shield, the second end disposed proximate the edge of the conductive shield. 17. The device of claim 12 , wher

Assignees

Inventors

Classifications

  • characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

  • Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

  • of die-attach connectors · CPC title

  • On different surfaces · CPC title

  • on encapsulations · CPC title

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11848288B2 cover?
In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a ce…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd, Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W44/501. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 19 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).