Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10083929-B2
Application number	US-201715666073-A
Country	US
Kind code	B2
Filing date	Aug 1, 2017
Priority date	Dec 16, 2016
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip, and at least one of the first connection member and the second connection member includes a dummy pattern layer.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a first connection member having a through-hole;
a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip,
wherein the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip,
the second connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip, and
at least one of the first connection member and the second connection member includes a first dummy pattern layer.

2. The fan-out semiconductor package of claim 1 , wherein the first dummy pattern layer is disposed above or below the coil pattern layer.

3. The fan-out semiconductor package of claim 1 , wherein at least a portion of the first dummy pattern layer is formed in the first connection member.

4. The fan-out semiconductor package of claim 2 , wherein the first dummy pattern layer is formed directly above or directly below the coil pattern layer.

5. The fan-out semiconductor package of claim 1 , wherein the first dummy pattern layer is electrically insulated from the coil pattern layer.

6. The fan-out semiconductor package of claim 1 , wherein the second connection member includes a second dummy pattern layer formed at a central portion of the coil pattern layer.

7. The fan-out semiconductor package of claim 6 , wherein the second dummy pattern layer is electrically insulated from the coil pattern layer.

8. The fan-out semiconductor package of claim 1 , wherein the coil pattern layer is formed in only a specific region of the first connection member.

9. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer in contact with the second connection member and embedded in a first surface of the first insulating layer, and a second redistribution layer disposed on a second surface of the first insulating layer opposing the first surface of the first insulating layer.

10. The fan-out semiconductor package of claim 9 , wherein the first connection member further includes a second insulating layer disposed on the first insulating layer and covering the second redistribution layer and a third redistribution layer disposed on the second insulating layer.

11. The fan-out semiconductor package of claim 9 , wherein a lower surface of the first redistribution layer has a step with respect to a lower surface of the first insulating layer.

12. The fan-out semiconductor package of claim 1 , wherein the first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer.

13. The fan-out semiconductor package of claim 12 , wherein the first connection member further includes a third insulating layer disposed on the first insulating layer and covering the second redistribution layer and a fourth redistribution layer disposed on the third insulating layer.

14. The fan-out semiconductor package of claim 12 , wherein the first insulating layer has a thickness greater than that of the second insulating layer.

15. A fan-out semiconductor package comprising:
a first connection member having a through-hole;
a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and
a second connection member disposed on the first connection member and the active surface of the semiconductor chip,
wherein the first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and
the second connection member includes a coil pattern layer electrically connected to the connection pads of the semiconductor chip and a first dummy pattern layer formed at a central portion of the coil pattern layer.

16. The fan-out semiconductor package of claim 15 , wherein at least one of the first connection member and the second connection member includes a second dummy pattern layer formed above or below the coil pattern layer.

17. The fan-out semiconductor package of claim 16 , wherein at least a portion of the second dummy pattern layer is formed in the first connection member.

Assignees

• Samsung Electro Mech

Inventors

• Choi Seong Hee
• Kim Han
• Park Dae Hyun
• Han Mi Ja

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/127

  characterised by arrangements for sealing or adhesion · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title