Semiconductor device

Patent metadata

Field	Value
Publication number	US-10115684-B2
Application number	US-201715424059-A
Country	US
Kind code	B2
Filing date	Feb 3, 2017
Priority date	Sep 29, 2014
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first semiconductor chip comprising:
a first plurality of wiring layers;
a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers; and
a first resin film formed over the uppermost layer of the first plurality of the wiring layers, a thickness of the first resin film being uniform between the first coil and the first dummy wires, and over top surfaces of the first coil and the first dummy wires; and

a second semiconductor chip comprising:
a second plurality of wiring layers;
a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers; and
a second resin film formed over the uppermost layer of the second plurality of the wiring layers, a thickness of the second resin film being uniform between the second coil and the second dummy wires, and over top surfaces of the second coil and the second dummy wires,

wherein the first semiconductor chip and the second semiconductor chip face each other via an insulation sheet,
wherein the first dummy wires are isolated from each other,
wherein the second dummy wires are isolated from each other, and
wherein the first coil and the second coil are magnetically coupled with each other.

2. The semiconductor device according to claim 1 , wherein the first semiconductor chip further comprises:
a first region in which the first coil and the first dummy wires are disposed; and
a second region in which the first bonding pad is disposed,
wherein the second semiconductor chip further comprises:
a third region in which the second coil and the second dummy wires are disposed; and

a fourth region in which the second bonding pad is disposed,
wherein the first region is overlapped with the third region in a plan view, and
wherein the second region is not overlapped with the fourth region in the plan view.

3. The semiconductor device according to claim 1 , wherein the first dummy wires are located around the first coil, and the second dummy wires are located around the second coil.

4. The semiconductor device according to claim 3 , wherein the first dummy wires are further located within the first coil, and the second dummy wires are further located within the second coil.

5. The semiconductor device according to claim 1 ,
wherein the insulation sheet comprises:
a first main surface bonded to the first resin film; and
a second main surface bonded to the second resin film.

6. A semiconductor device, comprising:
a first semiconductor chip comprising:
a first plurality of wiring layers;
a first coil formed in the first plurality of the wiring layers;
a first bonding pad and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers; and
a first resin film formed over the uppermost layer of the first plurality of the wiring layers, a thickness of the first resin film being uniform between the first coil and the first dummy wires, and over top surfaces of the first coil and the first dummy wires; and

a second semiconductor chip comprising:
a second plurality of wiring layers;
a second coil formed in the second plurality of the wiring layers; and
a second bonding pad and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers; and
a second resin film formed over the uppermost layer of the second plurality of the wiring layers, a thickness of the second resin film being uniform between the second coil and the second dummy wires, and over top surfaces of the second coil and the second dummy wires,

wherein the first semiconductor chip and the second semiconductor chip face each other via an insulation sheet,
wherein the first dummy wires are isolated from each other,
wherein the second dummy wires are isolated from each other, and
wherein the first coil and the second coil are magnetically coupled with each other.

7. The semiconductor device according to claim 6 , wherein the first semiconductor chip further comprises:
a first region in which the first coil and the first dummy wires are disposed; and
a second region in which the first bonding pad is disposed;
wherein the second semiconductor chip further comprises:
a third region in which the second coil and the second dummy wires are disposed; and
a fourth region in which the second bonding pad is disposed,

wherein the first region is overlapped with the third region in a plan view, and
wherein the second region is not overlapped with the fourth region in a plan view.

8. The semiconductor device according to claim 6 , wherein the first dummy wires are located around the first coil, and the second dummy wires are located around the second coil.

9. The semiconductor device according to claim 8 , wherein the first dummy wires are further located within the first coil, and the second dummy wires are further located within the second coil.

10. The semiconductor device according to claim 6 ,
wherein the insulation sheet comprises:
a first main surface bonded to the first resin film; and
a second main surface bonded to the second resin film.

11. The semiconductor device according to claim 1 , wherein a bottom surface of the first resin film abuts upper surfaces of the first dummy wires.

12. The semiconductor device according to claim 1 , wherein, in a plan view, the first dummy wires are located between the first coil and the second coil.

13. The semiconductor device according to claim 1 , wherein the first dummy wires are located within and around the first coil.

14. The semiconductor device according to claim 13 , wherein the second dummy wires are located within and around the second coil.

15. The semiconductor device according to claim 6 , wherein a bottom surface of the first resin film abuts upper surfaces of the first dummy wires.

16. The semiconductor device according to claim 6 , wherein, in a plan view, the first dummy wires are located between the first coil and the second coil.

17. The semiconductor device according to claim 6 , wherein the first dummy wires are located within and around the first coil.

18. The semiconductor device according to claim 17 , wherein the second dummy wires are located within and around the second coil.

Assignees

• Renesas Electronics Corp

Inventors

• Watanabe Shinpei
• Uchida Shinichi
• Maeda Tadashi
• Henmi Kazuo

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title