Method of manufacturing a semiconductor structure

Patent metadata

Field	Value
Publication number	US-10115685-B2
Application number	US-201815944463-A
Country	US
Kind code	B2
Filing date	Apr 3, 2018
Priority date	Oct 30, 2015
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A method of manufacturing a semiconductor structure includes providing a transceiver, forming a molding to surround the transceiver, forming a plurality of recesses extending through the molding, disposing a conductive material into the plurality of recesses to form a plurality of vias, disposing and patterning an insulating layer over the molding, the plurality of vias and the transceiver, and forming a redistribution layer (RDL) over the insulating layer, wherein the RDL comprises an antenna disposed over the insulating layer and a dielectric layer covering the antenna, and a portion of the antenna is extended through the insulating layer and is electrically connected with the transceiver.

First claim

The invention claimed is:

1. A method of manufacturing a semiconductor structure, comprising:
providing a transceiver;
forming a molding to surround the transceiver;
forming a plurality of recesses extending through the molding;
disposing a conductive material into the plurality of recesses to form a plurality of vias;
disposing and patterning an insulating layer over the molding, the plurality of vias and the transceiver; and
forming a redistribution layer (RDL) over the insulating layer;

wherein the RDL comprises an antenna disposed over the insulating layer and a dielectric layer covering the antenna, and a portion of the antenna is extended through the insulating layer and is electrically connected with the transceiver.

2. The method of claim 1 , further comprising forming a pillar extending from the insulating layer to the transceiver, and the antenna is electrically connected with the transceiver by the pillar.

3. The method of claim 1 , wherein the antenna is disposed by electroplating operations.

4. A method of manufacturing a semiconductor structure, comprising:
providing a transceiver;
forming a molding to surround the transceiver;
disposing a plurality of pillars extending through the molding towards the transceiver;
forming a patterned insulating layer over the molding, the plurality of pillars and the transceiver; and
disposing an antenna over the patterned insulating layer,

wherein the antenna is electrically connected with the transceiver through at least one of the plurality of pillars.

5. The method of claim 4 , wherein the disposing the plurality of pillars further comprises:
forming a plurality of recesses extending through the molding towards the transceiver; and
disposing a conductive material in the plurality of recesses to form the plurality of pillars.

6. The method of claim 4 , wherein the forming the patterned insulating layer further comprises:
disposing an insulating layer over the molding and the plurality of pillars; and
patterning the insulating layer to form the patterned insulating layer and to expose the plurality of pillars.

7. The method of claim 6 , wherein the antenna comprises an elongated portion extending over the patterned insulating layer and a via portion extending through the patterned insulating layer to electrically connect with the one of the plurality of pillars exposed through the patterned insulating layer.

8. The method of claim 4 , further comprising disposing a plurality of vias extending through the molding simultaneously with disposing the plurality of pillars.

9. The method of claim 8 , wherein a height of the plurality of pillars is less than a height of the plurality of vias.

10. A method of manufacturing a semiconductor structure, comprising:
providing a substrate;
disposing a transceiver over the substrate;
forming a molding over the substrate to surround the transceiver;
disposing a plurality of vias and a plurality of pillars in the molding;
forming a patterned insulating layer over the molding, the plurality of vias and the plurality of pillars; and
forming a RDL over the patterned insulating layer, the RDL comprising an antenna over the transceiver and the plurality of pillars,

wherein the antenna is electrically connected with the transceiver through the plurality of pillars.

11. The method of claim 10 , further comprising disposing a charger over the substrate before forming the molding.

12. The method of claim 10 , wherein the forming the plurality of vias and the plurality of pillars further comprises:
forming a plurality of first recesses extending through the molding to expose the substrate and a plurality of second recesses extending through the molding to expose the transceiver; and
disposing a conductive material in the plurality of first recesses to form the plurality of vias and in the plurality of second recesses to form the plurality of pillars.

13. The method of claim 12 , wherein a depth of the plurality of first recesses is greater than a depth of the plurality of second recesses.

14. The method of claim 10 , further comprising removing the substrate after forming the plurality of vias and the plurality of pillars.

15. The method of claim 10 , wherein the forming the patterned insulating layer further comprises:
disposing an insulating layer over the molding, the plurality of pillars and the plurality of vias: and
patterning the insulating layer to form the patterned insulating layer and to expose the plurality of pillars and a portion of the plurality of vias.

16. The method of claim 15 , wherein the antenna comprises an elongated portion extending over the patterned insulating layer and a via portion extending through the patterned insulating layer to electrically connect with at least one of the plurality of pillars exposed through the patterned insulating layer.

17. The method of claim 15 , wherein the RDL further comprises an interconnect structure, wherein the interconnect structure is electrically connected with the portion of the plurality of vias or the plurality of pillars exposed through the patterned insulating layer.

18. The method of claim 17 , wherein the interconnect structure is electrically connected with the transceiver through the plurality of pillars exposed through the patterned insulating layer.

19. The method of claim 18 , wherein the interconnect structure comprises an elongated portion extending over the patterned insulating layer and a via portion extending through the patterned insulating layer to the plurality of pillars exposed through the patterned insulating layer.

20. The method of claim 17 , wherein the RDL further comprises a dielectric layer surrounding the antenna and the interconnect structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Vincent
• Kuo Hung-Yi
• Wang Chuei-Tang
• Tsai Hao-Yi
• Yu Chen-Hua
• Chen Wei-Ting
• Tseng Ming Hung
• Lin Yen-Liang

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W44/248

  for antennas · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title