Methods for forming structures for MRAM applications

Patent metadata

Field	Value
Publication number	US-11818959-B2
Application number	US-202117379780-A
Country	US
Kind code	B2
Filing date	Jul 19, 2021
Priority date	Nov 19, 2018
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

First claim

What is claimed is:

1. A method of forming an interconnection structure comprising:
forming a film stack having a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer on a substrate;
forming a patterned hardmask layer on the film stack;
patterning the film stack using the patterned hardmask layer as an etching mask layer;
forming a first insulation material to cover the patterned hardmask layer and the film stack on the substrate;
polishing the first insulation material until a top surface of the patterned hardmask layer is exposed;
forming a spin orbit torque (SOT) layer on the top surface of the patterned hardmask layer; and
forming a first back end interconnection structure on the SOT layer.

2. The method of claim 1 , wherein the film stack and the patterned hardmask layer in combination form a magnetic tunnel junction structure.

3. The method of claim 1 , wherein the SOT layer is fabricated from the same material from the patterned hardmask layer.

4. The method of claim 1 , wherein the SOT layer and the patterned hardmask layer are fabricated from a material selected from a group consisting of CoFeB, MgO, Ta, W, Pt, CuBi, Mo and Ru.

5. The method of claim 1 , wherein the first back end interconnection structure is a dual damascene structure.

6. The method of claim 1 , wherein forming the SOT layer comprises:
forming a patterned insulating layer having an opening exposing the patterned hardmask layer; and
forming the SOT layer in the opening.

7. The method of claim 6 further comprising:
polishing the SOT layer and the patterned insulating layer so that a top surface of the SOT layer is substantially coplanar with the patterned insulating layer.

8. The method of claim 1 , wherein a lower interconnection structure is connected to the film stack.

9. The method of claim 8 , wherein the first back end interconnection structure is connected to the lower interconnection structure.

10. The method of claim 1 further comprising forming a second back end interconnection structure on the SOT layer.

11. A processing system comprising:
one or more processing chambers configured to:
form a film stack having a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer on a substrate;
form a patterned hardmask layer on the film stack;
pattern the film stack using the patterned hardmask layer as an etching mask layer;
form a first insulation material to cover the patterned hardmask layer and the film stack on the substrate;
polish the first insulation material until a top surface of the patterned hardmask layer is exposed;
form a spin orbit torque (SOT) layer on the top surface of the patterned hardmask layer; and
form a first back end interconnection structure on the SOT layer.

12. The processing system of claim 11 , wherein the film stack and the patterned hardmask layer in combination form a magnetic tunnel junction structure.

13. The processing system of claim 11 , wherein the SOT layer is fabricated from the same material from the patterned hardmask layer.

14. The processing system of claim 11 , wherein the SOT layer and the patterned hardmask layer are fabricated from a material selected from a group consisting of CoFeB, MgO, Ta, W, Pt, CuBi, Mo and Ru.

15. The processing system of claim 11 , wherein the first back end interconnection structure is a dual damascene structure.

16. The processing system of claim 11 , wherein forming the SOT layer comprises:
forming a patterned insulating layer having an opening exposing the patterned hardmask layer; and
forming the SOT layer in the opening.

17. The processing system of claim 16 , wherein the one or more processing chambers are further configured to:
polish the SOT layer and the patterned insulating layer so that a top surface of the SOT layer is substantially coplanar with the patterned insulating layer.

18. The processing system of claim 11 , wherein a lower interconnection structure is connected to the film stack.

19. The processing system of claim 18 , wherein the first back end interconnection structure is connected to the lower interconnection structure.

20. The processing system of claim 11 , wherein the one or more processing chambers is further configured to form a second back end interconnection structure on the SOT layer.

Assignees

• Applied Materials Inc

Inventors

• Tseng Hsin-Wei
• Park Chando
• Ahn Jaesoo
• Xue Lin
• Pakala Mahendra

Classifications

• H10B61/00 Primary

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/85

  Materials of the active region · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10N50/80 Primary

  Constructional details · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title