Bottom pinned sot-mram bit structure and method of fabrication

Patent metadata

Field	Value
Publication number	US-2017352702-A1
Application number	US-201715684892-A
Country	US
Kind code	A1
Filing date	Aug 23, 2017
Priority date	Oct 22, 2015
Publication date	Dec 7, 2017
Grant date	—

Abstract

Embodiments of the present disclosure generally relate to data storage and computer memory systems, and more particularly, to a SOT-MRAM chip architecture. The SOT-MRAM chip architecture includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having large spin-orbit coupling strength and high electrical resistivity. Each lead of the plurality of leads may include a plurality of first portions and a plurality of second portions distinct from the first portions. The electrical resistivity of the second portions is less than that of the first portions, so the total electrical resistivity of the lead is reduced, leading to improved power efficiency and signal to noise ratio.

First claim

What is claimed is:

1 . A spin-orbit torque magnetoresistive random access memory (SOT-MRAM) chip architecture, comprising:
a plurality of leads, wherein the leads are made of a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW; a plurality of memory cells coupled to each lead of the plurality of leads; and a plurality of transistors, wherein each transistor is coupled to a corresponding memory cell of the plurality of memory cells.

2 . The (SOT-MRAM) chip architecture of claim 1 , wherein each memory cell of the plurality of memory cells comprises a reference layer, a barrier layer, and a free layer.

3 . The (SOT-MRAM) chip architecture of claim 2 , wherein the free layer is in contact with the lead, and wherein a writing process is performed by a half-select mechanism that includes a combination of flowing a current along a lead of the plurality of leads and applying a voltage to a memory cell of the plurality of memory cells.

4 . The (SOT-MRAM) chip architecture of claim 2 , further comprising a spin-orbit torque layer disposed between the free layer of each memory cell and the lead.

5 . A (SOT-MRAM) chip architecture, comprising:
a plurality of leads, wherein each lead of the plurality of leads includes a plurality of first portions and a plurality of second portions distinct from the first portions, wherein each first portion of the plurality of first portions has a first width and each second portion of the plurality of second portions has a second width, and wherein the first width is smaller than the second width; a plurality of memory cells coupled to the first portions of each lead; and a plurality of transistors, wherein each transistor is coupled to a corresponding memory cell of the plurality of memory cells.

6 . The (SOT-MRAM) chip architecture of claim 5 , wherein each memory cell of the plurality of memory cells comprises a reference layer, a barrier layer, and a free layer.

7 . The (SOT-MRAM) chip architecture of claim 6 , wherein the free layer is in contact with a first portion of the plurality of first portions of the lead, and wherein a writing process is performed by a half-select mechanism that includes a combination of flowing a current along a lead of the plurality of leads and applying a voltage to a memory cell of the plurality of memory cells.

8 . The (SOT-MRAM) chip architecture of claim 6 , further comprising a spin-orbit torque layer disposed between the free layer of each memory cell and a first portion of the plurality of first portions of the lead.

9 . The (SOT-MRAM) chip architecture of claim 5 , wherein the lead is made of a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW.

10 . The (SOT-MRAM) chip architecture of claim 5 , wherein each first portion of the plurality of first portions is in contact with a memory cell of the plurality of memory cells and each second portion of the plurality of second portions is spaced from a memory cell of the plurality of memory cells.

11 . The (SOT-MRAM) chip architecture of claim 5 , wherein the first width ranges from about 10 nm to about 500 nm and the second width ranges from about 10 nm to about 500 nm.

12 . A (SOT-MRAM) chip architecture, comprising:
a plurality of leads, wherein each lead of the plurality of leads includes a plurality of first portions and a plurality of second portions distinct from the first portions, wherein each first portion of the plurality of first portions is made of a first material and each second portion of the plurality of second portions is made of a second material, and wherein the first material is different from the second material; a plurality of memory cells coupled to the first portions of each lead; and a plurality of transistors, wherein each transistor is coupled to a corresponding memory cell of the plurality of memory cells.

13 . The (SOT-MRAM) chip architecture of claim 12 , wherein each memory cell of the plurality of memory cells comprises a reference layer, a barrier layer, and a free layer.

14 . The (SOT-MRAM) chip architecture of claim 13 , wherein each first portion of the plurality of first portions is in contact with the free layer of a memory cell of the plurality of memory cells and each second portion of the plurality of second portions is spaced from a memory cell of the plurality of memory cells, and wherein a writing process is performed by a half-select mechanism that includes a combination of flowing a current along a lead of the plurality of leads and applying a voltage to a memory cell of the plurality of memory cells.

15 . The (SOT-MRAM) chip architecture of claim 13 , wherein each memory cell further comprises a spin-orbit torque layer disposed on the free layer, wherein each first portion of the plurality of first portions is in contact with the spin-orbit torque layer of a memory cell of the plurality of memory cells and each second portion of the plurality of second portions is spaced from a memory cell of the plurality of memory cells.

16 . The (SOT-MRAM) chip architecture of claim 12 , wherein the first material is selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW.

17 . The (SOT-MRAM) chip architecture of claim 16 , wherein the second material comprises copper, aluminum, or a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW that is doped with a dopant.

18 . The (SOT-MRAM) chip architecture of claim 16 , wherein the second material comprises one or more layers including at least one layer comprising copper, aluminum, or a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW that is doped with a dopant.

19 . The (SOT-MRAM) chip architecture of claim 18 , wherein the one or more layers include a first layer comprising copper, aluminum, and a second layer comprising a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW.

20 . The (SOT-MRAM) chip architecture of claim 12 , wherein:
each first portion of the plurality of first portions has a first width and each second portion of the plurality of second portions has a second width, the first width is smaller than the second width, and the first material is tantalum and the second material is tantalum doped with nitrogen.

Assignees

• Western Digital Tech Inc

Inventors

• Braganca Patrick M
• Tseng Hsin-Wei
• Wan Lei

Classifications

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/18

  using Hall-effect devices · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/10

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic