Microelectronic devices, memory devices, and electronic systems

Patent metadata

Field	Value
Publication number	US-11818893-B2
Application number	US-202217819009-A
Country	US
Kind code	B2
Filing date	Aug 11, 2022
Priority date	Aug 24, 2020
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.

First claim

What is claimed is:

1. A microelectronic device, comprising:
a stack structure comprising tiers each including conductive material and insulative material vertically adjacent the conductive material;
an array of cell pillar structures vertically extending through the stack structure;
an inverted staircase structure comprising horizontal ends of at least some of the tiers of the stack structure, relatively vertically higher steps of the inverted staircase structure horizontally positioned farther away from the array of cell pillar structures than relatively vertically lower steps of the inverted staircase structure;
a conductive routing tier vertically underlying the stack structure and comprising digit lines coupled to the array of cell pillar structures;
lateral contact structures vertically overlying the stack structure and coupled to the array of cell pillar structures;
control logic circuitry vertically overlying the lateral contact structures; and
contact structures coupled to the control logic circuitry and vertically extending from the control logic circuitry to the conductive routing tier.

2. The microelectronic device of claim 1 , wherein the control logic circuitry is at least partially positioned within a semiconductive wafer vertically overlying the lateral contact structures.

3. The microelectronic device of claim 2 , further comprising alignment mark structures vertically extending completely through the semiconductive wafer and individually having a different material composition than portions of the semiconductive wafer horizontally adjacent thereto, portions of the contact structures positioned within horizontal boundaries and vertical boundaries of the alignment mark structures.

4. The microelectronic device of claim 3 , further comprising an insulative isolation structure vertically extending partially though the semiconductive wafer and horizontally neighboring at least two of the alignment mark structures, the array of cell pillar structures positioned within a horizontal area of the insulative isolation structure.

5. The microelectronic device of claim 3 , wherein the alignment mark structures individually comprise semiconductive material.

6. The microelectronic device of claim 3 , wherein the alignment mark structures individually comprise insulative material.

7. The microelectronic device of claim 3 , wherein contact structures comprise:
first contact structures upwardly vertically extending from conductive routing structures within the conductive routing tier and partially into the alignment mark structures; and
second contact structures upwardly vertically extending from the first contact structures, through portions of the alignment mark structures overlying vertically upper boundaries of the first contact structures, and to additional conductive routing structures of the control logic circuitry.

8. The microelectronic device of claim 7 , wherein horizontal dimensions of the second contact structures are smaller than horizontal dimensions of the first contact structures.

9. The microelectronic device of claim 7 , further comprising insulative liner material covering side surfaces of the second contact structures, the insulative liner material horizontally interposed between conductive material of the second contact structures and semiconductive material of the alignment mark structures.

10. The microelectronic device of claim 1 , further comprising additional contact structures upwardly vertically extending from the conductive routing tier to the vertically higher steps and the vertically lower steps of the inverted staircase structure.

11. A memory device, comprising:
a semiconductive base structure having alignment mark structures extending therethrough;
a stack structure underlying the semiconductive base structure and comprising conductive structures vertically interleaved with insulative structures;
control logic circuitry partially overlying the semiconductive base structure and comprising transistors horizontally offset from the alignment mark structures;
an inverted staircase structure having steps comprising edges of the conductive structures of the stack structure;
semiconductive pillar structures horizontally offset from the inverted staircase structure and vertically extending through the stack structure, vertically lower ones of the steps of the inverted staircase structure positioned horizontally closer to the semiconductive pillar structures than vertically higher ones of the steps of the inverted staircase structure;
a conductive routing tier vertically underlying the semiconductive pillar structures and comprising:
digit line structures coupled to the semiconductive pillar structures; and
routing structures at a vertical position of the digit line structures;

contact structures within horizontal areas of the alignment mark structures and coupling the control logic circuitry to the routing structures; and
additional contact structures outside of the horizontal areas of the alignment mark structures and vertically extending from at least some of the steps of the inverted staircase structure to the routing structures.

12. The memory device of claim 11 , further comprising an isolation structure extending into the semiconductive base structure and horizontally interposed between two of the alignment mark structures, the isolation structure vertically interposed between the semiconductive pillar structures and a portion of the semiconductive base structure.

13. The memory device of claim 12 , further comprising a lateral contact structure vertically interposed between the isolation structure and the stack structure, the lateral contact structure in electrical communication with at least one of the routing structures and at least some of the semiconductive pillar structures.

14. The memory device of claim 13 , wherein:
the lateral contact structure vertically overlies upper boundaries of the alignment mark structures; and
the semiconductive pillar structures vertically extending completely through the lateral contact structure.

15. The memory device of claim 12 , further comprising a source structure extending into the isolation structure in electrical communication with at least some of the semiconductive pillar structure.

16. The memory device of claim 15 , wherein:
an upper boundary of the source structure is substantially coplanar with upper boundaries of the alignment mark structures; and
lower boundaries of the semiconductive pillar structures vertically overlie a lower boundary of the source structure.

17. The memory device of claim 15 , wherein the source structure horizontally overlaps of semiconductive pillar structures and is horizontally offset from all of the contact structures.

18. The memory device of claim 17 , wherein the source structure is horizontally offset from at least some of the steps of the inverted staircase structure and from at least some of the additional contact structures.

19. An electronic system, comprising:
a processor device operably connected to an input device and an output device; and
a memory device operably connected to the processor device and comprising:
a stack structure comprising conductive structures and insulative structures vertically alternating with the conductive structures;
strings of memory cells vertically extending through the stack structure;
an inverted staircase structure having steps comprising horizontal ends of at least some of the conductive structures of the stack structure, relatively vertically higher one

Assignees

• Micron Technology Inc

Inventors

• Meotto Umberto Maria
• Camerlenghi Emilio
• Tessariol Paolo
• Laurin Luca

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title