Memory structures and related cross-point memory arrays, electronic systems, and methods of forming memory structures

Patent metadata

Field	Value
Publication number	US-9397145-B1
Application number	US-201514712241-A
Country	US
Kind code	B1
Filing date	May 14, 2015
Priority date	May 14, 2015
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A memory structure comprises first conductive lines extending in a first direction over portions of a base structure, storage element structures extending in the first direction over the first conductive lines, isolated electrode structures overlying portions of the storage element structures, select device structures extending in a second direction perpendicular to the first direction over the isolated electrode structures, second conductive lines extending in the second direction over the select device structures, additional select device structures extending in the second direction over the second conductive lines, additional isolated electrode structures overlying portions of the additional select device structures, additional storage element structures extending in the first direction over the additional isolated electrode structures, and third conductive lines extending in the first direction over the additional storage element structures. Cross-point memory arrays, electronic systems, and related methods are also described.

First claim

What is claimed is:

1. A memory structure, comprising:
first conductive lines extending in a first direction over portions of a base structure;
storage element structures extending in the first direction over the first conductive lines;
isolated electrode structures overlying portions of the storage element structures;
select device structures extending in a second direction perpendicular to the first direction over the isolated electrode structures;
second conductive lines extending in the second direction over the select device structures;
additional select device structures extending in the second direction over the second conductive lines;
additional isolated electrode structures overlying portions of the additional select device structures;
additional storage element structures extending in the first direction over the additional isolated electrode structures; and
third conductive lines extending in the first direction over the additional storage element structures.

2. The memory structure of claim 1 , further comprising:
buffer structures between the first conductive lines and the storage element structures and extending in the first direction; and
additional buffer structures between the additional storage element structures and the third conductive lines and extending in the first direction.

3. The memory structure of claim 2 , wherein at least one of the buffer structures and the additional buffer structures comprise at least one of an ion reservoir material, a solid electrolyte ion conductor material, and an ion diffusion barrier material.

4. The memory structure of claim 2 , wherein lower surfaces and opposing sidewalls of the additional buffer structures are surrounded by the additional storage element structures.

5. The memory structure of claim 1 , further comprising dielectric structures extending in the first direction over other portions of the base structure and located laterally between the first conductive lines, the storage element structures, and the isolated electrode structures.

6. The memory structure of claim 5 , further comprising additional dielectric structures extending in the second direction over portions of the dielectric structures and other portions of the storage element structures and located laterally between the isolated electrode structures, the select device structures, the second conductive lines, the additional select device structures, and the additional isolated electrode structures.

7. The memory structure of claim 1 , wherein at least one of the storage element structures and the additional storage element structures comprises a resistance variable material.

8. The memory structure of claim 1 , wherein at least one of the storage element structures and the additional storage element structures comprises an oxide material.

9. The memory structure of claim 1 , wherein at least one of the storage element structures and the additional storage element structures comprises elevated peripheral portions and recessed central portions.

10. The memory structure of claim 1 , wherein at least one of the storage element structures and the additional storage element structures comprise damascene structures.

11. The memory structure of claim 1 , wherein lower surfaces and opposing sidewalls of the isolated electrode structures are surrounded by the storage element structures.

12. The memory structure of claim 1 , wherein lower surfaces and opposing sidewalls of the third conductive lines are surrounded by the additional storage element structures.

13. A method of forming a memory structure, comprising:
forming first conductive lines extending in a first direction within trenches located between dielectric structures overlying a base structure;
forming storage element structures over the first conductive lines within the trenches;
forming electrode structures over the storage element structures within the trenches;
forming a material stack over the dielectric structures and the electrode structures, the material stack comprising a select device material, a conductive line material over the select device material, an additional select device material over the conductive line material, an electrode material over the additional select device material, and a masking material over the electrode material;
forming openings through the material stack and the electrode structures to form isolated electrode structures, select device structures over portions of the dielectric structures and the isolated electrode structures, second conductive lines over the select device structures, additional select device structures over the second conductive lines, and additional electrode structures over the additional select device structures, the openings extending in a second direction perpendicular to the first direction;
forming additional dielectric structures over other portions of the dielectric structures and the storage element structures within the openings;
forming sacrificial structures over portions of the additional electrode structures and the additional dielectric structures, the sacrificial structures separated from one another by additional trenches extending in the first direction;
forming additional storage element structures over other portions of the additional electrode structures and the additional dielectric structures within the additional trenches;
forming third conductive lines over the additional storage element structures within the additional trenches; and
removing the sacrificial structures and the portions of the additional electrode structures under the sacrificial structures to from additional isolated electrode structures.

14. The method of claim 13 , further comprising:
forming buffer structures between the first conductive lines and the storage element structures within the trenches; and
forming additional buffer structures between the additional storage element structures and the third conductive lines within the additional trenches.

15. The method of claim 13 , further comprising forming the storage element structures and the electrode structures substantially simultaneously.

16. The method of claim 15 , wherein forming the storage element structures and the electrode structures substantially simultaneously comprises:
forming a storage element material over the first conductive lines and the dielectric structures;
forming a conductive material over storage element material; and
performing a polishing process to remove portions of the conductive material and the storage element material outside of the trenches.

17. The method of claim 13 , wherein forming openings through the material stack and the electrode structures comprises removing portions of the material stack and the electrode structures without removing portions of the storage element structures underlying the portions of the material stack and the electrode structures.

18. The method of claim 13 , wherein forming openings through the material stack and the electrode structures comprises forming the openings using a single photolithographic patterning process.

19. The method of claim 13 , wherein forming sacrificial structures over portions of the additional electrode structures and the additional dielectric structures comprises:
forming a sacrificial material over additional electrode structures and the additional dielectric structures; and
forming the additional trenches in the sacrificial material.

20. The method of claim 13 , further comprising forming the additional storage

Assignees

• Micron Technology Inc

Inventors

• Sills Scott E
• Ramaswamy D V Nirmal

Classifications

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• H01L45/06

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/1246

  Electricity · mapped topic

• H01L27/24

  Electricity · mapped topic