Systems and devices including multi-transistor cells and methods of using, making, and operating the same

Patent metadata

Field	Value
Publication number	US-9449652-B2
Application number	US-201314010089-A
Country	US
Kind code	B2
Filing date	Aug 26, 2013
Priority date	Mar 20, 2008
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A device may include a first transistor, a second transistor, and a data element. The first transistor may have a column gate and a channel, and the second transistor may include a row gate that crosses over the column gate, under the column gate, or both. The second transistor may also include another channel, a source disposed near a distal end of a first leg, and a drain disposed near a distal end of a second leg. The column gate may extend between the first leg and the second leg. The channel of the second transistor may be connected to the channel of the first transistor, and the data element may be connected to the source or the drain. Methods, systems, and other devices are contemplated.

First claim

What is claimed is:

1. A device, comprising:
a plurality of data cells, wherein each data cell comprises:
a first transistor comprising:
a column gate; and
a first channel;

a second transistor comprising:
a row gate, wherein the row gate crosses over the column gate, under the column gate, or both;
a source disposed near a distal end of a first leg;
a drain disposed near a distal end of a second leg, wherein the column gate extends between the first leg and the second leg;
a second channel, wherein the second channel of the second transistor is connected to the first channel of the first transistor; and

a data element connected to the source or the drain.

2. The device of claim 1 , wherein the data element comprises a memory element or an imaging element.

3. The device of claim 1 , wherein the second channel of the second transistor comprises a pair of channels connected by the first channel of the first transistor.

4. The device of claim 1 , wherein the row gate crosses over the column gate.

5. The device of claim 1 , wherein the row gate crosses under the column gate.

6. The device of claim 1 , wherein the row gate crosses both over the column gate and under the column gate.

7. A method, comprising:
forming a first gate in a trench;
after forming the first gate in the trench, forming a plurality of laterally spaced and longitudinally elongated fins individually extending generally perpendicular to the first gate; and
forming a second gate that crosses over the first gate.

8. The method of claim 7 , wherein forming the fins forms a cuboid volume between immediately adjacent of the fins.

9. The method of claim 7 , wherein forming the fins removes some conductive material of the first gate.

10. The method of claim 7 , wherein forming the fins etches into some conductive material of the first gate.

11. The method of claim 7 , wherein individual of the fins are formed to be longitudinally continuous along an individual row line.

12. A method, comprising:
forming a pair of laterally spaced and immediately laterally adjacent isolation trenches in a substrate;
forming a first gate disposed between the pair of isolation trenches and laterally outward of each isolation trench of the pair of isolation trenches;
forming a longitudinally elongated opening that crosses over the first gate and the pair of isolation trenches; and
forming two second gates within the opening and which cross over the first gate and the pair of isolation trenches.

13. The method of claim 12 , comprising completely filing the isolation trenches with dielectric material prior to forming the first gate.

14. The method of claim 12 , comprising forming the two second gates to be mirror image of one another.

15. A method, comprising:
forming a pair of laterally spaced and immediately laterally adjacent isolation trenches in a substrate;
forming a first gate disposed between the pair of isolation trenches and laterally outward of each isolation trench of the pair of isolation trenches; and
forming a second gate overlapping the first gate and the pair of isolation trenches, the forming of the second gate comprising a sidewall spacer process whereby conductive material is deposited over sidewalls and laterally all across a base of an opening followed by anisotropic etching of the conductive material to remove some of the conductive material from being over the base of the opening.

16. The method of claim 15 , comprising forming two of said second gates within the opening.

17. The method of claim 15 , comprising forming the second gate to cross over the first gate.

18. A method, comprising:
forming a pair of laterally spaced and immediately laterally adjacent isolation trenches in a substrate;
forming a first gate disposed between the pair of isolation trenches and laterally outward of each isolation trench of the pair of isolation trenches; and;
forming a second gate that crosses over the first gate and the pair of isolation trenches, the second gate having a conductive elevationally innermost surface that is lower than a conductive elevationally outermost surface of the first gate.

Assignees

• Micron Technology Inc

Inventors

• Juengling Werner

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• G11C11/405

  with three charge-transfer gates, e.g. MOS transistors, per cell · CPC title

• H01L29/785

  Electricity · mapped topic