Memory devices having signal routing structures at bonding interfaces
US-2024404976-A1 · Dec 5, 2024 · US
Nonvolatile memory device
US9515083B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9515083-B2 |
| Application number | US-201514723296-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 27, 2015 |
| Priority date | Sep 19, 2014 |
| Publication date | Dec 6, 2016 |
| Grant date | Dec 6, 2016 |
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Abstract
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A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a first metal layer, a peripheral circuit configured to control the memory cell array, a second metal layer, and a pad. The first metal layer is disposed on the memory cell array and includes a plurality of cell region interconnections connected to the memory cell array. The second metal layer is disposed on the peripheral circuit and includes a plurality of peripheral region interconnections connecting the peripheral circuit and the plurality of cell region interconnections. The pad is disposed on the second metal layer and exchanges data, an address, or a command with the peripheral circuit during operation of the device. The second metal layer is lower than the first metal layer relative to a substrate of the device.
First claim
Opening claim text (preview).
What is claimed is: 1. A nonvolatile memory device, comprising: a memory cell array including a plurality of memory cells; a first metal layer on the memory cell array and including a plurality of cell region interconnections connected to the memory cell array; a peripheral circuit configured to control the memory cell array; a second metal layer on the peripheral circuit and including a plurality of peripheral region interconnections connecting the peripheral circuit and th…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9515083B2 cover?
- A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a first metal layer, a peripheral circuit configured to control the memory cell array, a second metal layer, and a pad. The first metal layer is disposed on the memory cell array and includes a plurality of cell region interconnections connected to the memory cell array. The second metal layer is dis…
- Who is the assignee on this patent?
- Lee Jae-Eun, Kim Sunghoon, Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10B43/40. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).