Apparatus and method for controlling access to a memory device

Patent metadata

Field	Value
Publication number	US-2016357688-A1
Application number	US-201514731638-A
Country	US
Kind code	A1
Filing date	Jun 5, 2015
Priority date	Jun 5, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

An apparatus and method are provided for controlling access to a memory device. The apparatus has a pending access requests storage that is used to store access requests waiting to be issued to the memory device, and memory access control circuitry is then used to issue to the memory device access requests selected from the pending access requests storage. Access requests are received at an interface of the apparatus from at least one requesting device, and access request evaluation circuitry within the apparatus is arranged to apply criteria to determine, for a current access request, whether to accept that current access request or reject that current access request. The criteria applied takes account of at least one access timing characteristic of the memory device. The access request evaluation circuitry is responsive to determining that the current access request is to be accepted, to cause that current access request to be stored in the pending access requests storage. However, if instead the access request is rejected, it is prevented from being added to the pending access requests storage at that time, and instead a rejection indication is issued to the requesting device that issued that current access request. This provides a mechanism for significantly improving the performance of the memory device by providing more selectivity as to what access requests are accepted into the pending access requests storage.

First claim

We claim:

1 . An apparatus for controlling access to a memory device, comprising:
a pending access requests storage to store access requests to be issued to the memory device; memory access control circuitry to issue to the memory device access requests selected from the pending access requests storage; an interface to receive access requests from at least one requesting device; and access request evaluation circuitry to apply criteria to determine, for a current access request received by said interface, whether to accept that current access request, the criteria taking account of at least one access timing characteristic of the memory device; the access request evaluation circuitry being responsive to determining that the current access request is to be accepted, to cause that current access request to be stored in the pending access requests storage.

2 . An apparatus as claimed in claim 1 , wherein:
the access request evaluation circuitry is responsive to determining from application of the criteria that the current access request is to be rejected instead of accepted, to prevent that current access request being added to the pending access requests storage and to cause a rejection indication to be issued to the requesting device that issued that current access request.

3 . An apparatus as claimed in claim 1 , wherein:
the access request evaluation circuitry is arranged to compare at least one attribute of the current access request with at least one attribute of access requests in the pending access requests storage when applying the criteria to take account of said at least one access timing characteristic of the memory device.

4 . An apparatus as claimed in claim 3 , wherein the memory device comprises a plurality of regions, and said at least one attribute comprises a region attribute identifying a region of the memory device to be accessed by the access request.

5 . An apparatus as claimed in claim 4 , wherein said at least one access timing characteristic of the memory device comprises a data access timing penalty incurred when the memory access control circuitry issues access requests to the memory device that identify different regions.

6 . An apparatus as claimed in claim 5 , wherein the access request evaluation circuitry is arranged to determine that the current access request is to be rejected when it is determined that the addition of the current access request to the pending access requests storage could give rise to said data access timing penalty being incurred when that current access request is subsequently issued to the memory device, having regard to the access requests already stored in the pending access requests storage.

7 . An apparatus as claimed in claim 5 , wherein the plurality of regions comprise a plurality of ranks.

8 . An apparatus as claimed in claim 7 , wherein the data access timing penalty is incurred when the memory access control circuitry issues consecutive write access requests to different ranks within the memory device.

9 . An apparatus as claimed in claim 5 , wherein the plurality of regions comprise a plurality of rows within a bank of the memory device, and the data access timing penalty is incurred when the memory access control circuitry issues access requests to different rows within the same bank of the memory device.

10 . An apparatus as claimed in claim 4 , wherein said at least one access timing characteristic of the memory device comprises an access time period associated with a particular type of access request already stored in the pending access requests storage.

11 . An apparatus as claimed in claim 10 , wherein the access request evaluation circuitry is arranged to determine that the current access request is to be rejected when it is determined that the current access request is seeking to access a region that is the same as the region to be accessed by said particular type of access request already stored in the pending access requests storage.

12 . An apparatus as claimed in claim 11 , wherein the current access request is rejected when the particular type of access request already stored in the pending access requests storage has been issued by the memory access control circuitry to the memory device, but the memory device has not yet completed processing of that access request.

13 . An apparatus as claimed in claim 1 , further comprising:
control storage to store control data used to determine whether the access request evaluation circuitry is enabled for the current access request, when the access request evaluation circuitry is disabled the current access request being accepted and stored within the pending access requests storage.

14 . An apparatus as claimed in claim 13 , wherein the control data identifies at least a fullness threshold of the pending access requests storage, and the access request evaluation circuitry is disabled for the current access request if the number of access requests already stored in the pending access requests storage does not exceed said fullness threshold.

15 . An apparatus as claimed in claim 14 , wherein the control data additionally identifies one or more additional criteria to be evaluated when determining whether the access request evaluation circuitry is enabled for the current access request.

16 . An apparatus as claimed in claim 2 , further comprising:
retry control circuitry to apply retry criteria to determine whether to issue to a requesting device a retry request, in order to cause said requesting device to re-issue to the apparatus an access request that has previously been rejected, the retry criteria taking account of at least one access timing characteristic of the memory device.

17 . An apparatus as claimed in claim 16 , wherein:
the retry control circuitry is arranged to analyse at least one attribute of access requests in the pending access requests storage when applying the retry criteria to take account of said at least one access timing characteristic of the memory device.

18 . An apparatus as claimed in claim 17 , further comprising:
a rejected access requests storage to maintain predetermined information about access requests that have previously been rejected, said predetermined information comprising at least said at least one attribute that is analysed by the retry control circuitry for the access requests in the pending access requests storage.

19 . An apparatus as claimed in claim 18 , wherein the retry control circuitry is arranged to determine, from the analysis of said at least one attribute of access requests in the pending access requests storage, a value of said at least one attribute desired for a re-issued access request, and is arranged to reference the rejected access requests storage to determine whether the access requests that have been previously rejected include an access request having that value for said at least one attribute.

20 . An apparatus as claimed in claim 16 , wherein said retry request includes an identifier field identifying at least one attribute required for the access request to be re-issued.

21 . An apparatus as claimed in claim 20 , wherein said rejection indication issued by the access request evaluation circuitry when an access request is rejected also includes said identifier field, allowing said at least one requesting device to maintain a record of its access requests that have been rejected, sorted by said at least one attribute.

22 . An apparatus as claimed in cl

Assignees

• Advanced Risc Mach Ltd

Inventors

• Brittain Mark Andrew
• Campbell Michael Andrew

Classifications

• G06F13/1631 Primary

  through address comparison · CPC title

• G06F13/18

  based on priority control (G06F13/1605 takes precedence) · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F12/1441 Primary

  for a range · CPC title

• G06F2212/1024

  Latency reduction · CPC title