Memory location determining device and method for determining locations of compressed data in a memory by using first and second arithmetic operations

Patent metadata

Field	Value
Publication number	US-9519599-B2
Application number	US-201314091122-A
Country	US
Kind code	B2
Filing date	Nov 26, 2013
Priority date	Jun 10, 2011
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A memory location determining device determines memory locations for storing M pieces of compressed data each of which is compressed from one of M pieces of N-bit data. For each piece of compressed data, the memory location determining device performs a first arithmetic operation on an address value of a corresponding piece of N-bit data, and determines to store X bits of the piece of compressed data and a flag indicating whether or not the piece of compressed data exceeds X bits at a location indicated by the result value of the first arithmetic operation. When the piece of compressed data exceeds X bits, the memory location determining device further performs a second arithmetic operation on the address value of the corresponding piece of N-bit data and determines to store one or more bits of the piece of compressed data other than the X bits.

First claim

The invention claimed is:

1. A memory location determining device for determining locations in a memory, the locations for storing M pieces of compressed data each compressed from a corresponding one of M pieces of N-bit data to be less than N bits, the M pieces of N-bit data constituting a data block, the memory location determining device comprising:
a judgment unit configured to judge, for each of the M pieces of compressed data, whether a piece of compressed data is ordinary compressed data or special compressed data, the ordinary compressed data having a length of X bits or less, where X<N, the special compressed data having a length of Y bits, where Y>X;
a division unit configured to, with respect to each of the M pieces of compressed data, when the judgment unit judges that the piece of compressed data is special compressed data, divide the piece of compressed data being the special compressed data into first compressed data having a length of X bits and second compressed data having a length of Y−X bits;
a first determiner configured to
perform, for each of the M pieces of compressed data, a first arithmetic operation on an address value of a corresponding piece of N-bit data in the data block, and
determine a location indicated by a result value of the first arithmetic operation as a location for storing first data of the piece of compressed data, the first data having a length of L bits or less, where L<N,
wherein when the piece of compressed data is ordinary compressed, where X<L<N, the first data includes all bits of the piece of ordinary compressed data and a flag indicates that the length is X bits or less, and
wherein when the piece of compressed data is special compressed data, the first data includes the first compressed data and a flag indicating that the length exceeds X bits; and

a second determiner configured to
perform, for each piece of special compressed data, a second arithmetic operation on the address value of the corresponding piece of N-bit data in the data block, and
determine a location indicated by a result value of the second arithmetic operation as a location for storing second data of the piece of special compressed data, the second data including the second compressed data,
wherein the second arithmetic operation is selected from a plurality of second arithmetic operations based on a status of one or more pieces of special compressed data among the M pieces of compressed data.

2. The memory location determining device according to claim 1 , wherein:
each result value of the first arithmetic operation indicates a different location in a first area of the memory, and
each result value of the second arithmetic operation indicates a location in a second area of the memory, the second area being contiguous with the first area.

3. The memory location determining device according to claim 2 , wherein:
the first area is a (N×M/2)-bit area,
each flag is an F-bit flag,
each piece of special compressed data has a length exceeding N/2−F bits, and
the first determiner performs, for each of the M pieces of compressed data, a division by 2 of the address value of the corresponding piece of N-bit data in the data block and determines a location indicated by a result value of the division as the location for storing the first data of the piece of the compressed data.

4. The memory location determining device according to claim 3 , wherein:
when the second area is a (N×M/4)-bit area, and out of the respective address values of the M pieces of N-bit data in the data block, each two address values are taken as a set,
one second arithmetic operation is selected among the plurality of second arithmetic operations, and
for each set of two address values, the one second arithmetic operation yields two result values each indicating a location starting N/2 bits apart from a location indicated by the other result value.

5. The memory location determining device according to claim 3 , wherein:
when the second area is a (N×⅜)-bit area, and out of the respective address values of the M pieces of N-bit data in the data block, each four address values are taken as a set,
a group of three second arithmetic operations is selected among the plurality of second arithmetic operations, and
for each set of four address values, the group of three second arithmetic operations yields three result values,
as the location for storing the second data of a piece of special compressed data in the set, the second determiner determines one out of the three locations indicated by the three result values yielded for the set, the one location not for storing the second data of any other piece of special compressed data in the set, and
the flag included in the first data of the piece of special compressed data is a two-bit flag indicating the one location determined for storing the second data out of the three locations.

6. The memory location determining device according to claim 1 , wherein:
when out of the respective address values of the M pieces of N-bit data in the data block, each J address values are taken as a set, where K≦J≦M,
one or more second arithmetic operations are selected,
when performed on any address value in one set, the first arithmetic operation as well as the one or more second arithmetic operations yields a result value indicating a location in a first area of the memory, and
when performed on any address value in another set, the first arithmetic operation as well as the one or more second arithmetic operations yields a result value indicating a location in a second area of the memory, the second area differing from the first area.

7. The memory location determining device according to claim 6 , wherein:
the J address values in each set are four consecutive address values out of the respective address values of the M pieces of N-bit data in the data block,
when performed on each of a first address value and a second address value both included in the one set, the one or more second arithmetic operations yields a common result value indicating a common location that is one sub-area of the first area,
when performed on each of a third address value and a fourth address value both included in the one set, the one or more second arithmetic operations yields a common result value indicating a common location that is N/2 bits apart from the location indicated by the result value yielded by the one or more second arithmetic operations performed on the first and second address values, and
when performed on any address value in the one set, the first arithmetic operation yields a result value indicating a location different within the first area from any of the locations indicated by the result values yielded by the one or more second arithmetic operations performed on the first, second, third, and fourth address values.

8. A method for determining locations in a memory, the locations for storing M pieces of compressed data each compressed from a corresponding one of M pieces of N-bit data to be less than N bits, the M pieces of N-bit data constituting a data block, the method comprising:
a judging step of, for each of the M pieces of compressed data, judging whether a piece of compressed data is ordinary compressed data or special compressed data, the ordinary compressed data having a length of X bits or less, where X<N, the special compressed data having a length of Y bits, where Y>X;
a dividing step of, with respect to each of the M pieces of compressed data, when it is judged that the piece of compressed data is special compressed data, dividing the piece of compressed data being the special compressed data into first compressed data having a length of X bits and second compressed data having a length of Y−X bi

Assignees

• Panasonic Corp
• Panasonic Ip Man Co Ltd

Inventors

• Matsuyama Shinya

Classifications

• G06F13/1631 Primary

  through address comparison · CPC title

• G06F9/30178

  of compressed or encrypted instructions · CPC title

• H03M7/6058

  Saving memory space in the encoder or decoder · CPC title

• H03M7/4031

  Fixed length to variable length coding · CPC title

• G06F12/04

  Addressing variable-length words or parts of words · CPC title