Compute near memory with backend memory

Patent metadata

Field	Value
Publication number	US-11812599-B2
Application number	US-202217670248-A
Country	US
Kind code	B2
Filing date	Feb 11, 2022
Priority date	Mar 23, 2020
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

First claim

What is claimed is:

1. A method of forming a gain cell memory device comprising:
forming over a first substrate, a first region comprising a word line driver, a read circuitry, and active fins;
forming a dielectric region over the first region;
forming at least one storage region in the dielectric region;
forming a layer of at least one write circuit in contact with the at least one storage region;
bonding a structure onto a surface of the dielectric region; and
removing the first substrate to expose the active fins.

2. The method of claim 1 , comprising:
forming in the first region one or more of: read (MR) transistors, vias, redistribution structures, metal routing, power supplies, memory controllers, memory management units, row decoder and drivers, and/or processing circuitry.

3. The method of claim 1 , wherein:
forming the dielectric region over the first region comprises including one or more of: silicon dioxide (SiO2), carbon doped oxide (CDO), silicon nitride, perfluorocyclobutane, polytetrafluoroethylene, fluorosilicate glass (FSG), silsesquioxane, siloxane, organosilicate glass, a silicon oxide (SiO) film, a silicon nitride (SiN) film, O3-tetraethylorthosilicate (TEOS), O3-hexamethyldisiloxane (HMDS), or plasma-TEOS oxide layer.

4. The method of claim 1 , wherein:
forming the dielectric region over the first region comprises including pores or air gaps.

5. The method of claim 1 , wherein:
forming at least one storage region in the dielectric region comprises forming at least one capacitor in contact with the dielectric region.

6. The method of claim 1 , wherein:
the at least one storage region comprises a Capacitor Over Bitline (COB).

7. The method of claim 1 , wherein:
forming the layer of at least one write circuit in contact with the at least one storage region comprises forming a layer of at least one write circuit with one or more of: Poly-Si, Si, Ge, poly-Ge, III-V, GaN, MoS2, WSe2, MoSe2, WSe2, InS, HfS, ZnS, ZnSe, In2O3, ZnO, AZO, IGZO, or IZO.

8. The method of claim 1 , wherein the at least one write circuit comprises at least one non-silicon-based write circuit.

9. The method of claim 1 , wherein:
forming the layer of at least one write circuit in contact with the at least one storage region comprises:
forming a first layer with a drain region;
forming a channel layer;
forming a gate oxide layer;
forming a gate layer with a write word line interface; and
forming a source region with a write bit line interface.

10. The method of claim 1 , wherein:
forming the layer of at least one write circuit in contact with the at least one storage region comprises:
forming a channel region;
forming a gate oxide region over a portion of the channel region;
forming a gate region over a portion of the gate oxide region;
forming a source region over a portion of the channel region; and
forming a drain region over a portion of the channel region.

11. The method of claim 1 , wherein:
forming the layer of at least one write circuit in contact with the at least one storage region comprises:
forming a channel region;
forming a source region formed under a portion of the channel region;
forming a drain region formed under a portion of the channel region;
forming a gate oxide region formed over a portion of the channel region; and
forming a gate region formed over a portion of the gate oxide region.

12. The method of claim 1 , comprising:
forming a wordline circuitry within the structure.

13. The method of claim 1 , comprising:
bonding a second substrate onto a surface of the structure.

14. The method of claim 13 , wherein:
bonding the second substrate onto the surface of the structure comprises applying a bonding material to opposing surfaces of the second substrate and the surface of the structure and contacting the bonding material applied to opposing surfaces.

15. The method of claim 14 , wherein:
the bonding material comprises one or more of: silicon dioxide (SiO2), silicon oxynitride (SiON), carbon doped-silicon oxynitride (SiOCN), silicon carbon nitride (SiCN), or silicon oxycarbide (SiOC).

16. The method of claim 1 , wherein:
removing the first substrate to expose the active fins comprises one or more of: etching, polishing, or grinding.

17. The method of claim 16 , comprising:
forming one or more layers on top of the exposed active fins.

18. The method of claim 17 , wherein the one or more layers comprise one or more of: bitline signal routing to a sense amplifier (SA), wordline drivers, silicon transistors used in connection with a memory array, read circuitry, write circuitry, multiplex circuitry, or decode circuitry.

Assignees

• Intel Corp

Inventors

• Sharma Abhishek
• Sato Noriyuki
• Atanasov Sarah
• Sumbul Huseyin Ekin
• Chen Gregory K
• Knag Phil
• Krishnamurthy Ram
• Yoo Hui Jae
• Le Van H

Classifications

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/0214

  using temporary substrates · CPC title