Metal-insulator-metal (MIM) capacitor with insulator stack having a plurality of metal oxide layers

Patent metadata

Field	Value
Publication number	US-9691839-B2
Application number	US-201113996494-A
Country	US
Kind code	B2
Filing date	Dec 14, 2011
Priority date	Dec 14, 2011
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a plurality of semiconductor devices disposed in or above a substrate;
one or more dielectric layers disposed above the plurality of semiconductor devices;
metal wiring disposed in each of the dielectric layers and electrically coupled to one or more of the semiconductor devices; and
a metal-insulator-metal (MIM) capacitor disposed in a trench disposed in at least one of the dielectric layers, adjacent to the metal wiring of the at least one of the dielectric layers, the MIM capacitor electrically coupled to one or more of the semiconductor devices and comprising:
a first metal plate disposed along the bottom and sidewalls of the trench, the first metal plate comprising a first inner cup-shaped conductive layer disposed on a first outer cup-shaped conductive layer, wherein the first inner cup-shaped conductive layer is separate and distinct from the first outer cup-shaped conductive layer;
an insulator stack disposed above and conformal with the first metal plate, the insulator stack comprising a first metal oxide layer conformal with and in contact with the first metal plate and comprising titanium oxide, a second metal oxide layer conformal with and in contact with the first metal oxide layer and comprising hafnium oxide or zirconium oxide, and a third metal oxide layer conformal with and in contact with the second metal oxide layer and comprising titanium oxide; and
a second metal plate disposed above and conformal with and in contact with the third metal oxide layer of the insulator stack, the second metal plate comprising a second outer cup-shaped conductive layer disposed on a second inner cup-shaped conductive layer, wherein the second outer cup-shaped conductive layer is separate and distinct from the second inner cup-shaped conductive layer, and wherein the second metal oxide layer of the insulator stack is not in contact with the first metal plate and is not in contact with the second metal plate.

2. The semiconductor structure of claim 1 , wherein at least a portion of the metal wiring is electrically coupled to one or more semiconductor devices included in a logic circuit, and wherein the MIM capacitor is an embedded dynamic random access memory (eDRAM) capacitor.

3. The semiconductor structure of claim 1 , wherein the MIM capacitor is disposed in only one of the dielectric layers.

4. The semiconductor structure of claim 1 , wherein the MIM capacitor is disposed in only two of the dielectric layers, adjacent to the metal wiring of each of the two dielectric layers and also adjacent to a via coupling the metal wiring of each of the two dielectric layers.

5. The semiconductor structure of claim 1 , wherein the MIM capacitor is disposed in more than two of the dielectric layers, adjacent to the metal wiring of all of the more than two dielectric layers.

6. The semiconductor structure of claim 1 , wherein the sidewalls of the trench comprise a vertical or near-vertical profile.

7. The semiconductor structure of claim 1 , wherein the sidewalls of the trench taper outward from the bottom of the at least one of the dielectric layers to the top of the at least one of the dielectric layers.

8. The semiconductor structure of claim 1 , wherein the thickness of the second metal oxide layer is approximately three times the thickness of each of the first and third metal oxide layers.

9. A semiconductor structure, comprising:
a plurality of semiconductor devices disposed in or above a substrate;
one or more dielectric layers disposed above the plurality of semiconductor devices;
metal wiring disposed in each of the dielectric layers and electrically coupled to one or more of the semiconductor devices; and
a metal-insulator-metal (MIM) capacitor disposed in a trench disposed in at least one of the dielectric layers, adjacent to the metal wiring of the at least one of the dielectric layers, the MIM capacitor electrically coupled to one or more of the semiconductor devices and comprising:
a first metal plate disposed along the bottom and sidewalls of the trench;
an insulator stack disposed above and conformal with the first metal plate, the insulator stack comprising a first metal oxide layer conformal with and in contact with the first metal plate and comprising titanium oxide, a second metal oxide layer conformal with and in contact with the first metal oxide layer and comprising hafnium oxide or zirconium oxide, and a third metal oxide layer conformal with and in contact with the second metal oxide layer and comprising titanium oxide; and

a second metal plate disposed above and conformal with and in contact with the third metal oxide layer of the insulator stack, wherein the second metal oxide layer of the insulator stack is not in contact with the first metal plate and is not in contact with the second metal plate.

10. The semiconductor structure of claim 9 , wherein at least a portion of the metal wiring is electrically coupled to one or more semiconductor devices included in a logic circuit, and wherein the MIM capacitor is an embedded dynamic random access memory (eDRAM) capacitor.

11. The semiconductor structure of claim 9 , wherein the MIM capacitor is disposed in only one of the dielectric layers.

12. The semiconductor structure of claim 9 , wherein the MIM capacitor is disposed in only two of the dielectric layers, adjacent to the metal wiring of each of the two dielectric layers and also adjacent to a via coupling the metal wiring of each of the two dielectric layers.

13. The semiconductor structure of claim 9 , wherein the MIM capacitor is disposed in more than two of the dielectric layers, adjacent to the metal wiring of all of the more than two dielectric layers.

14. The semiconductor structure of claim 9 , wherein the sidewalls of the trench comprise a vertical or near-vertical profile.

15. The semiconductor structure of claim 9 , wherein the sidewalls of the trench taper outward from the bottom of the at least one of the dielectric layers to the top of the at least one of the dielectric layers.

16. The semiconductor structure of claim 9 , wherein the thickness of the second metal oxide layer is approximately three times the thickness of each of the first and third metal oxide layers.

17. An embedded metal-insulator-metal (MIM) capacitor for a semiconductor device, the capacitor comprising:
a trench disposed in a dielectric layer disposed above a substrate;
a first metal plate disposed along the bottom and sidewalls of the trench;
an insulator stack disposed above and conformal with the first metal plate, the insulator stack comprising a first metal oxide layer conformal with and in contact with the first metal plate and comprising titanium oxide, a second metal oxide layer conformal with and in contact with the first metal oxide layer and comprising hafnium oxide or zirconium oxide, and a third metal oxide layer conformal with and in contact with the second metal oxide layer and comprising titanium oxide; and
a second metal plate disposed above and conformal with the insulator stack.

18. The embedded MIM capacitor of claim 17 , wherein the second metal oxide layer comprises hafnium oxide.

19. The embedded MIM capacitor of claim 17 , wherein the second metal oxide layer comprises zirconium oxide.

20. The embedded MIM capacitor of claim 17 , wherein the first metal oxide layer has a thickness approximately in the range of 0.5-20 nanometers.

21. The embedded MIM capacitor of claim 17 , wherein the thickness of the s

Assignees

• Lindert Nick
• Glassman Timothy E
• Baran Andre
• Intel Corp

Inventors

• Lindert Nick
• Glassman Timothy E
• Baran Andre

Classifications

• H10B12/31

  having a storage electrode stacked over the transistor · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/696 Primary

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H01L27/108

  Electricity · mapped topic