Method and apparatus for improved integrated circuit temperature evaluation and IC design

Patent metadata

Field	Value
Publication number	US-9323870-B2
Application number	US-201313874925-A
Country	US
Kind code	B2
Filing date	May 1, 2013
Priority date	May 1, 2012
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A method and apparatus generates thermal partitions for metal interconnects of an integrated circuit, based on interconnect self heat data and mutual heat data. Each of the thermal partitions includes data identifying thermally related interconnects and respective temperature values associated with each of the thermally related interconnects. Thermally related partitions that can be computed efficiently and simultaneously and the results then integrated using superposition for the full chips.

First claim

What is claimed is:

1. A method, performed by an apparatus, for determining integrated circuit (IC) thermal values for metal interconnects of the IC comprising:
generating thermal partitions for metal interconnects of the integrated circuit, based on interconnect self heat data and mutual heat data, wherein each of the thermal partitions comprises data identifying thermally related interconnects and respective temperature values associated with each of the thermally related interconnects;
wherein generating thermal partitions comprises:
determining a per interconnect temperature for an interconnect of interest using the interconnect self heat data and mutual heat data from interconnects at a desired distance from the interconnect for all interconnects per interconnect layer;
forming a thermal region that is comprised of aggressor interconnects to the interconnect of interest when the interconnect temperature is determined to be above a threshold;
repeating the determining and forming operation to produce multiple thermal regions; and
combining intersecting regions that have a common interconnect to form a thermal partition.

2. The method of claim 1 wherein generating thermal partitions for metal interconnects of the integrated circuit comprises generating interconnect self heat data and mutual heat data; receiving integrated circuit or package parameters and wherein the method comprises determining whether thermal violations occur in a partition.

3. The method of claim 1 wherein the thermal partitions comprise a set of interconnect segments that influence each other based on a desired threshold and wherein the method comprises generating a plurality of partitions for the integrated circuit.

4. The method of claim 1 wherein the thermal partitions comprise segment material information, dielectric information, boundary condition information of a partition including boundary temperature information and power information per segment.

5. The method of claim 4 comprising displaying thermal information corresponding to the thermal partitions for metal interconnects of the integrated circuit whose thermal level is beyond a desired threshold.

6. The method of claim 1 comprising conducting a thermal analysis of the thermal partitions for metal interconnects of the integrated circuit; and displaying thermal information corresponding to the thermal partitions for metal interconnects of the integrated circuit to facilitate a design change in the interconnect layout of the integrated circuit.

7. An apparatus for determining integrated circuit thermal values for metal interconnects comprising logic operative to generate thermal partitions for metal interconnects of the integrated circuit, based on interconnect self heat data and mutual heat data, wherein each of the thermal partitions comprises data identifying thermally related interconnects and respective temperature values associated with each of the thermally related interconnects;
wherein the logic is operative to generate thermal partitions by:
determining a per interconnect temperature for an interconnect of interest using the interconnect self heat data and mutual heat data from other interconnects from the interconnect for all interconnects per interconnect layer;
forming a thermal region that is comprised of aggressor interconnects to the interconnect of interest when the interconnect temperature is determined to be above a threshold:
repeating the determining and forming operation to produce multiple thermal regions; and
combining intersecting regions that have a common interconnect to form a thermal partition.

8. The apparatus of claim 7 wherein the logic is operative to generate thermal partitions by generating interconnect self heat data and mutual heat data; receiving integrated circuit or package parameters and wherein the method comprises determining whether thermal violations occur in a partition.

9. The apparatus of claim 7 wherein the thermal partitions comprise a set of interconnect segments that influence each other based on a desired threshold.

10. The apparatus of claim 7 wherein the thermal partitions comprise segment material information, dielectric information, boundary condition information of a partition including boundary temperature information and power information per segment.

11. The apparatus of claim 7 wherein the logic is operative to conduct a thermal analysis of the thermal partitions for metal interconnects of the integrated circuit; and display the thermal information corresponding to the thermal partitions for metal interconnects of the integrated circuit to facilitate a design change in the interconnect layout of the integrated circuit.

12. A non-transitory computer readable medium comprising executable instructions stored therein that when executed by one or more processors, causes the one or more processors to: generate thermal partitions for metal interconnects of the integrated circuit, based on interconnect self heat data and mutual heat data, wherein each of the thermal partitions comprises data identifying thermally related interconnects and respective temperature values associated with each of the thermally related interconnects and to generate thermal partitions by:
determining a per interconnect temperature for an interconnect of interest using the interconnect self heat data and mutual heat data from other interconnects at a desired distance from the interconnect for all interconnects per interconnect layer;
forming a thermal region that is comprised of aggressor interconnects to the interconnect of interest when the interconnect temperature is determined to be above a threshold;
repeating the determining and forming operation to produce multiple thermal regions; and
combining intersecting regions that have a common interconnect to form a thermal partition.

Assignees

• Advanced Micro Devices Inc

Inventors

• Chandra Rajit C

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• G06F30/30 Primary

  Circuit design · CPC title

• G06F30/23 Primary

  using finite element methods [FEM] or finite difference methods [FDM] · CPC title

• G06F17/50 Primary

  Physics · mapped topic