Runtime virtualization of reconfigurable data flow resources

Patent metadata

Field	Value
Publication number	US-11809908-B2
Application number	US-202016922975-A
Country	US
Kind code	B2
Filing date	Jul 7, 2020
Priority date	Jul 7, 2020
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.

First claim

What is claimed is:

1. A data processing system, comprising:
a pool of reconfigurable data flow resources, the reconfigurable data flow resources in the pool of reconfigurable data flow resources including arrays of physical configurable units and memory, the arrays of physical configurable units comprising physical compute units and physical memory units of a coarse-grained reconfigurable processor; and
a runtime processor operatively coupled to the pool of reconfigurable data flow resources, the runtime processor including logic to:
receive a plurality of configuration files for user applications, the configuration files in the plurality of configuration files including configurations of virtual data flow resources mapped to individual applications of the user applications, the virtual data flow resources representing functionality of physical configurable units required to execute the user applications;
allocate the physical configurable units and the memory in the pool of reconfigurable data flow resources to the virtual data flow resources, and load the configuration files to the allocated physical configurable units; and
execute the user applications using the allocated physical configurable units and memory;

wherein the runtime processor runs in a host processor operatively coupled to the pool of reconfigurable data flow resources, wherein the runtime processor includes a runtime library that runs in a userspace of the host processor and a kernel module that runs in a kernelspace of the host processor, and wherein the kernel module includes a resource manager and a driver;
the runtime library passes a file descriptor identifying the configurations of virtual data flow resources to the kernel module using an input-output control (IOCTL) system call;
wherein the resource manager uses the file descriptor to allocate the reconfigurable data flow resources to the virtual data flow resources and returns a context structure identifying the allocated reconfigurable data flow resources to the runtime library; and
wherein the runtime library is configured with logic to execute a configuration load process that includes generating a dynamic state profile based on the configurations of virtual data flow resources and progressively traversing states of the dynamic state profile, the states including at least one of loading the configuration files, loading arguments modifying the configuration files, loading virtual memory segments supporting the configuration files, beginning execution of the configuration files, pausing execution of the configuration files, and unloading the configurations files after execution.

2. A data processing system, comprising:
a pool of reconfigurable data flow resources including arrays of physical configurable units in at least one coarse-grained reconfigurable processor, the arrays of physical configurable units including physical compute units and physical memory units; and
a runtime processor operatively coupled to the pool of reconfigurable data flow resources, the runtime processor including logic to:
receive configuration files for computation graphs comprising nodes and edges, the configuration files including metadata binding memory fragments of the computation graphs to virtual memory units and binding compute fragments of the computation graphs to virtual compute units, and bit files required to execute the computation graphs,
wherein the virtual memory units and the virtual compute units are identified in the metadata of the configuration files,
wherein a memory fragment comprises one or more address calculations leading up to a memory access defined by a particular computation graph, and
wherein a compute fragment comprises one or more compute operations defined by the particular computation graph;

allocate respective physical compute units and physical memory units in the pool of reconfigurable data flow resources to the identified virtual compute units and the identified virtual memory units;
load the bit files of the configuration files to the allocated physical compute units and the allocated physical memory units; and
execute the computation graphs using the allocated physical compute units and physical memory units configured with the bit files.

3. The data processing system of claim 2 , wherein the runtime processor includes logic to return the allocated physical compute units and physical memory units for an executed computation graph to the pool of reconfigurable data flow resources for reallocation to another computation graph.

4. The data processing system of claim 2 , wherein a compiler generates the configuration files and sends the configuration files to the runtime processor via an application programming interface.

5. The data processing system of claim 2 , wherein the metadata specifies one or more arrays in the arrays of physical configurable units required to execute the computation graphs.

6. The data processing system of claim 5 , wherein the metadata specifies one or more subarrays of the one or more arrays.

7. The data processing system of claim 6 , wherein the metadata specifies topology of the one or more subarrays of the one or more arrays.

8. The data processing system of claim 2 , wherein the pool of reconfigurable data flow resources includes bus interfaces.

9. The data processing system of claim 8 , wherein the bus interfaces include one or more of peripheral component interconnect express (PCIe) channels, direct memory access (DMA) channels, double data rate (DDR) channels, or network access channels.

10. The data processing system of claim 2 , wherein the pool of reconfigurable data flow resources includes memory subsystems, separate from the physical memory units in the arrays of physical configurable units, the memory subsystems comprising main memory of the runtime processor, external memory controlled by the at least one coarse-grained reconfigurable processor, local secondary storage, and/or remote secondary storage.

11. The data processing system of claim 10 , wherein the metadata specifies virtual memory segments for the memory, including virtual address spaces of the virtual memory segments and sizes of the virtual address spaces.

12. The data processing system of claim 11 , wherein the runtime processor maps the virtual address spaces of the virtual memory segments to physical address spaces of physical memory segments in the memory.

13. The data processing system of claim 12 , wherein the runtime processor configures control and status registers of the at least one coarse-grained reconfigurable processor with configuration data identifying the mapping between the virtual address spaces and the physical address spaces to allow the physical compute units and/or physical memory units to access the physical memory segments during execution of the computation graphs.

14. The data processing system of claim 13 , wherein a first set of the physical memory segments mapped to a first memory subsystem allocated to a first computation graph are different from a second set of the physical memory segments mapped to a second memory subsystem allocated to a second computation graph.

15. The data processing system of claim 14 , wherein access of the first memory subsystem is confined to the first set of the physical memory segments, and access of the second memory subsystem is confined to the second set of the physical memory segments.

16. The data processing system of claim 2 , wherein the runtime processor runs in a host processor operatively coupled to the pool of reconfigurable data flow resources, wherein the runtime proc

Assignees

• Sambanova Systems Inc

Inventors

• Kumar Ravinder
• Turlik Conrad Alexander
• Goel Arnav
• Zheng Qi
• Shenbagam Raghunath
• Misra Anand
• Vayyala Ananda Reddy

Classifications

• G06F2209/5011

  Pool · CPC title

• G06F9/5011 Primary

  the resources being hardware resources other than CPUs, Servers and Terminals · CPC title

• G06F9/5016

  the resource being the memory · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title