Frequency error estimation and pilot spacing in orthogonal frequency division multiplexing systems.
US-2026095360-A1 · Apr 2, 2026 · US
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Kumar Ravinder patents
Kumar Ravinder is listed as an inventor on 74 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kumar Ravinder |
| Total patents | 74 |
| First publication | Nov 23, 2021 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Configurable access to a reconfigurable processor by a virtual function
US-12572342-B2 · Mar 10, 2026 · US
Intelligent graph execution for a reconfigurable data processor
US-2026056913-A1 · Feb 26, 2026 · US
Handling interrupts from a virtual function in a system with a Multi-Die reconfigurable processor
US-12554473-B2 · Feb 17, 2026 · US
Configurable access to a multi-die reconfigurable processor by a virtual function
US-12547389-B2 · Feb 10, 2026 · US
Doppler clustering techniques for per cluster parameter estimation and cluster detection
US-2026029527-A1 · Jan 29, 2026 · US
Method for Providing Runtime Virtualization of Reconfigurable Data Flow Resources
US-2025377935-A1 · Dec 11, 2025 · US
Physical broadcast channel for channel correction
US-2025374305-A1 · Dec 4, 2025 · US
Techniques for performing tracking using a physical broadcast channel
US-2025365683-A1 · Nov 27, 2025 · US
Intelligent graph execution and orchestration engine for a reconfigurable data processor
US-12461889-B2 · Nov 4, 2025 · US
Recent patents
Latest publications not already listed above.
Data processing system with link-based resource allocation for reconfigurable processors
US-12413530-B2 · Sep 9, 2025 · US
Method and apparatus for data transfer between accessible memories of multiple processors in a heterogeneous processing system using two memory to memory transfer operations
US-12380041-B2 · Aug 5, 2025 · US
Physical broadcast channel for channel correction
US-12362871-B2 · Jul 15, 2025 · US
Runtime virtualization of reconfigurable data flow resources
US-12346729-B2 · Jul 1, 2025 · US
Handling interrupts from a virtual function in a system with a reconfigurable processor
US-12340195-B2 · Jun 24, 2025 · US
Load balancing system for the execution of applications on reconfigurable processors
US-12298932-B2 · May 13, 2025 · US
Data access in a heterogeneous processing system with multiple processors
US-2025117336-A1 · Apr 10, 2025 · US
Decoding metadata encoded in error correction codes
US-12261623-B2 · Mar 25, 2025 · US
Direct access to reconfigurable processor memory
US-12242403-B2 · Mar 4, 2025 · US
Method and apparatus for selecting data access method in a heterogeneous processing system with multiple processors
US-12229057-B2 · Feb 18, 2025 · US
Data transfer between accessible memories of multiple processors incorporated in coarse-grained reconfigurable (CGR) architecture within heterogeneous processing system using one memory to memory transfer operation
US-12210468-B2 · Jan 28, 2025 · US
Symbol rotation of cache line codewords for increased reliability with metadata
US-12181971-B1 · Dec 31, 2024 · US
Symbol rotation of cache line codewords for increased reliability with metadata
US-2024419550-A1 · Dec 19, 2024 · US
Method and apparatus for data access in a heterogeneous processing system with multiple processors using memory extension operation
US-12169459-B2 · Dec 17, 2024 · US
Decoding metadata encoded in error correction codes
US-2024380415-A1 · Nov 14, 2024 · US
Intelligent graph execution and orchestration engine for a reconfigurable data processor
US-2024338340-A1 · Oct 10, 2024 · US
Data processing system with link-based resource allocation for reconfigurable processors
US-2024330074-A1 · Oct 3, 2024 · US
Optimized subframe blanking for dual sim dual active
US-2024292401-A1 · Aug 29, 2024 · US
Method and apparatus for data transfer between accessible memories of multiple processors in a heterogeneous processing system using one memory to memory transfer operation
US-2024248863-A1 · Jul 25, 2024 · US
Method and apparatus for data access in a heterogeneous processing system with multiple processors using memory extension operation
US-2024248853-A1 · Jul 25, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Sambanova Systems Inc | 61 |
| Qualcomm Inc | 9 |
| Microsoft Technology Licensing Llc | 4 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F15/7871 | 28 |
| G06F9/45558 | 27 |
| G06F9/5077 | 25 |
| G06F2009/4557 | 19 |
| G06F9/44505 | 19 |