Gate structure and method with enhanced gate contact and threshold voltage

Patent metadata

Field	Value
Publication number	US-11804547-B2
Application number	US-202117410769-A
Country	US
Kind code	B2
Filing date	Aug 24, 2021
Priority date	Nov 29, 2017
Publication date	Oct 31, 2023
Grant date	Oct 31, 2023

Abstract

The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor substrate having a first region and a second region being adjacent to the first region;
first fins formed on the semiconductor substrate within the first region, wherein the first fins are longitudinally oriented along a first direction and disposed with a spacing d1 along a second direction being different from the first direction, and wherein a number of the first fins is greater than 5;
a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region, wherein the STI feature continuously extends to fill up the second region and spans a dimension d2 within the second region along the second direction, wherein d2 is greater than d1; and
a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment disposed directly on the first STI feature within the second region, wherein the second segment of the first gate stack includes a first tantalum titanium nitride layer, a titanium aluminum nitride layer, a second tantalum titanium nitride layer, and a low resistance metal (LRM) layer stacked in sequence, wherein the first segment of the first gate stack within the first region is free of the LRM layer.

2. The semiconductor structure of claim 1 , wherein
a ratio d2/d1 is greater than 5;
each of the first fins has an elongated shape oriented in the first direction and spans a width w along the second direction;
the first gate stack has another elongated shape oriented in the second direction; and
the dimension d2 is substantially greater than the width w.

3. The semiconductor structure of claim 2 , wherein
the first segment of the first gate stack with the first region includes the first tantalum titanium nitride layer and the titanium aluminum nitride layer; and
the first segment of the first gate stack within the first region further defines a void surrounded by the titanium aluminum nitride layer.

4. The semiconductor structure of claim 1 , wherein the first segment of the first gate stack within the first region has a first length L1 at a top surface, a second length L2 at a middle and a third length L3 at a bottom surface, wherein L2 is greater L1 and L3 is greater than L2, wherein L1, L2 and L3 are dimensions along the first direction.

5. The semiconductor structure of claim 4 , wherein the first segment of the first gate stack within the first region has a fourth length L4 above the middle at a level to a top surface of the first fins, L4 being less than L1.

6. The semiconductor structure of claim 5 , wherein a first ratio of L1/L4 is greater than 1.1; a second ratio of L2/L4 is greater than 1.2; and a third ratio of L3/L4 is greater than 1.4.

7. The semiconductor structure of claim 1 , wherein the LRM layer includes at least one of tungsten, copper, aluminum, and copper aluminum alloy.

8. The semiconductor structure of claim 1 , wherein
each of one of the first fins further includes an n-type channel region underlying the first gate stack;
the n-type channel region is doped of a p-type dopant; and
the second direction is orthogonal to the first direction.

9. The semiconductor structure of claim 8 , further comprising:
second fins formed on the semiconductor substrate within a third region;
a second STI feature disposed on the semiconductor substrate within a fourth region; and
a second gate stack disposed directly on the second fins, wherein the second gate stack is free of the LRM layer and the second tantalum titanium nitride layer.

10. The semiconductor structure of claim 9 , wherein the tantalum aluminum nitride layer of the second gate stack is shaped with a void defined therein.

11. The semiconductor structure of claim 9 , further comprising a p-type channel region underlying the second gate stack and formed in the second fins, wherein the p-type channel region is doped of an n-type dopant.

12. The semiconductor structure of claim 11 , wherein
first source and drain features formed on the first fins, interposed by the n-type channel region, wherein the first gate stack, the first source and drain features, and the n-type channel are configured to an n-type field-effect transistor (nFET); and
second source and drain features formed on the second fins, interposed by the p-type channel region, wherein the second gate stack, the second source and drain features, and the p-type channel are configured to a p-type field-effect transistor (pFET).

13. The semiconductor structure of claim 1 , wherein
the first tantalum titanium nitride layer in the second segment of the first gate stack is shaped to surround the titanium aluminum nitride layer from bottom and sidewalls;
the titanium aluminum nitride layer in the second segment of the first gate stack is shaped to surround the second tantalum titanium nitride layer from bottom and sidewalls; and
the second tantalum titanium nitride layer in the second segment of the first gate stack is shaped to surround the LRM layer from bottom and sidewalls.

14. A semiconductor structure, comprising:
a semiconductor substrate having a first region for n-type transistors and a second region for p-type transistors;
first fins disposed on the semiconductor substrate within the first region and second fins disposed on the semiconductor substrate within the second region;
a first gate stack disposed directly on the first fins, wherein the first gate stack includes a first tantalum titanium nitride layer, a second tantalum titanium nitride layer, a titanium aluminum nitride layer sandwiched between the first and second tantalum titanium nitride layers, and a low resistance metal (LRM), wherein the first gate stack includes a first elongate shape oriented along a first direction, and wherein a first number of the first fins is 2; and
a second gate stack disposed directly on the second fins, wherein the second gate stack is free of the LRM and includes the first tantalum titanium nitride layer and the titanium aluminum nitride layer, wherein the LRM is different from the first and second tantalum titanium nitride layers and the titanium aluminum nitride layer in composition, wherein the second gate stack includes a second elongate shape oriented along the first direction, wherein the first and second gate stacks are distanced away in a second direction that is orthogonal to the first direction, and wherein a second number of the second fins is greater than 5.

15. The semiconductor structure of claim 14 , further comprising:
an n-type channel region formed on the first fins, wherein the n-type channel region is doped with a p-type dopant and is underlying the first gate stack;
a p-type channel region formed on the second fins, wherein the p-type channel region is doped with an n-type dopant and is underlying the second gate stack;
first source and drain features formed on the first fins, interposed by the n-type channel region, wherein the first gate stack, the first source and drain features, and the n-type channel are configured to an n-type field-effect transistor (nFET); and
second source and drain features formed on the second fins, interposed by the p-type channel region, wherein the second gate stack, the second source and drain features, and the p-type channel are configured to a p-type field-effect transistor (pFET).

16. The semiconductor structure of claim 15 , wherein
each of the first fins has an elongated shape oriented in a first direction; and
the first gate stack has a first length L1 at a top surface, a second length L2 at a mid

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Max
• Peng Yen-Ming
• Ho Wei-Shuo

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P14/3444

  P-type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title