Systems for reverse pulsing

Patent metadata

Field	Value
Publication number	US-11798785-B2
Application number	US-201715701176-A
Country	US
Kind code	B2
Filing date	Sep 11, 2017
Priority date	Aug 5, 2015
Publication date	Oct 24, 2023
Grant date	Oct 24, 2023

Abstract

Systems and methods for reverse pulsing are described. One of the systems includes a controller, first and second source radio frequency (RF) generators, and first and second bias RF generators. The controller controls the first source RF generator to generate a first source pulsed signal, and controls the second source RF generator to generate a second source pulsed signal. The system includes a first match circuit that receives the first and second source pulsed signals and combines the first and second source pulsed signals. The controller controls the first bias RF generator to generate a first bias pulsed signal, and controls the second bias RF generator to generate a second bias pulsed signal. The system includes a second match circuit that receives the first and second bias pulsed signals and combines the first and second bias pulsed signals into a combined bias signal.

First claim

The invention claimed is:

1. A system comprising:
a computer configured to generate a digital pulsed signal having a high bit state and a low bit state;
a source radio frequency (RF) generator coupled to the computer via a shared cable located between the computer and the source RF generator, wherein the source RF generator includes a processor and a source power supply, wherein the processor of the source RF generator is configured to receive the digital pulsed signal from the computer via the shared cable, wherein in response to the reception of the digital pulsed signal, the processor of the source RF generator is configured to control the source power supply to generate a source RF pulsed signal having a first high state and a low state in synchronization with the digital pulsed signal, wherein the first high state of the source RF pulsed signal has a greater amount of power than the low state of the source RF pulsed signal;
a plasma chamber coupled to the source RF generator, wherein the plasma chamber is associated with a top coil electrode and has a bottom electrode, wherein the source RF generator is coupled to the top coil electrode; and
a bias RF generator coupled to the computer via the shared cable located between the computer and the bias RF generator, wherein the bias RF generator includes a processor and a bias power supply, wherein the processor of the bias RF generator is configured to receive the digital pulsed signal via the shared cable, wherein the bias RF generator is coupled to the bottom electrode, wherein in response to the reception of the digital pulsed signal, the processor of the bias RF generator is configured to control the bias power supply to generate a bias RF pulsed signal in reverse synchronization with the digital pulsed signal, wherein the bias RF pulsed signal is generated to have the low state for a first time period during which the digital pulsed signal is in the high bit state, wherein the bias RF pulsed signal has a second high state for a second time period during which the digital pulsed signal is in the low bit state, wherein the second time period is equal to the first time period, wherein the second high state of the bias RF pulsed signal has a greater amount of power than the low state of the bias RF pulsed signal,
wherein the computer is configured to:
control the source RF generator to transition the source RF pulsed signal from the first high state to the low state at a time of transition of the digital pulsed signal from the high bit state to the low bit state, and
control the bias RF generator to transition the bias RF pulsed signal from the low state to the second high state at the time of transition of the digital pulsed signal from the high bit state to the low bit state, wherein the bias RF pulsed signal transitions from the low state to the second high state during a conductor etch to control directionality of ions of plasma and to reduce a temperature of electrons within the plasma,
wherein the processor of the bias RF generator is configured to determine that the digital pulsed signal transitions from the high bit state to the low bit state, and send a control signal to the bias power supply to transition the bias RF pulsed signal from the low state to the second high state in response to determining that the digital pulsed signal transitions from the high bit state to the low bit state.

2. The system of claim 1 , wherein the top coil electrode is one or more RF coils, and the bottom electrode is a chuck of the plasma chamber.

3. The system of claim 1 ,
wherein to control the source RF generator to generate the source RF pulsed signal, the computer is configured to control the source RF generator to:
transition the source RF pulsed signal from the low state to the first high state within a predetermined amount of time from a transition of the digital pulsed signal from the low bit state to the high bit state,

wherein to control the bias RF generator to generate the bias RF pulsed signal, the computer is configured to control the bias RF generator to:
transition the bias RF pulsed signal from the second high state to the low state within the predetermined amount of time from the transition of the digital pulsed signal from the low bit state to the high bit state.

4. The system of claim 1 ,
wherein to control the source RF generator to generate the source RF pulsed signal, the computer is configured to control the source RF generator to:
transition the source RF pulsed signal from the low state to the first high state at a time of a transition of the digital pulsed signal from the low bit state to the high bit state.

5. The system of claim 4 , wherein to generate the bias RF pulsed signal, the computer is configured to control the bias RF generator to:
transition the bias RF pulsed signal from the second high state to the low state at the time of the transition of the digital pulsed signal from the low bit state to the high bit state.

6. The system of claim 1 , wherein the source RF pulsed signal has zero power during the low state of the source RF pulsed signal and a positive amount of power during the first high state of the source RF pulsed signal.

7. The system of claim 6 , wherein the bias RF pulsed signal has zero power during the low state of the bias RF pulsed signal and a positive amount of power during the second high state of the bias RF pulsed signal.

8. The system of claim 1 ,
wherein the source RF generator synchronizes each additional transition of the source RF pulsed signal with a corresponding one of a plurality of transitions of the digital pulsed signal,
wherein the bias RF generator synchronizes each additional transition of the bias pulsed RF signal with the corresponding one of a plurality of transitions of the digital pulsed signal.

9. The system of claim 1 , wherein the processor of the source RF generator is configured to receive the digital pulsed signal from the computer, determine that the digital pulsed signal transitions from the high bit state to the low bit state, and send a control signal to the source power supply to transition the source RF pulsed signal from the first high state to the low state.

10. A system comprising:
a host computer configured to generate a digital signal;
a source radio frequency (RF) generator including a processor coupled to the host computer via a shared cable to receive the digital signal from the host computer via the shared cable, wherein the source RF generator includes a source power supply, wherein the shared cable is located between the host computer and the source RF generator, wherein the digital signal periodically transitions between a high bit state and a low bit state;
a first match circuit coupled to the source RF generator;
a plasma chamber associated with a top coil electrode and having a bottom electrode, wherein the top coil electrode is coupled to the first match circuit,
wherein in response to the reception of the digital pulsed signal, the processor of the source RF generator is configured to control the source power supply to generate a source RF pulsed signal in synchronization with the digital signal to provide the source RF pulsed signal to the first match circuit, wherein the source RF pulsed signal has a low state and a first high state, wherein the first high state of the source RF pulsed signal has a greater amount of power than the low state of the source RF pulsed signal;
a bias RF generator including a processor and a bias power supply, wherein the processor of the bias RF generator is coupled to the host computer via the shared cable to receive the digital signal from the host computer via the shared cable, wherein the shared cable is located be

Assignees

• Lam Res Corp

Inventors

• Long Maolin
• Tan Zhongkui
• Wu Ying
• Fu Qian
• Paterson Alex
• Drewery John

Classifications

• H10P72/0421

  for drying etching · CPC title

• H10P50/242 Primary

  of Group IV materials · CPC title

• H10P72/00

  Handling or holding of wafers, substrates or devices during manufacture or treatment thereof · CPC title

• H10P72/04

  Apparatus for manufacture or treatment · CPC title

• H01J2237/334

  Etching · CPC title