SSL/GSL gate oxide in 3D vertical channel NAND

Patent metadata

Field	Value
Publication number	US-9559113-B2
Application number	US-201414267493-A
Country	US
Kind code	B2
Filing date	May 1, 2014
Priority date	May 1, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A memory device includes an array of strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. A plurality of vertical active strips is formed between the plurality of stacks. Charge storage structures are formed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes and the vertical active strips in the plurality of vertical active strips. Gate dielectric, having a different composition than the charge storage structures, is formed in interface regions at cross-points between the vertical active strips and side surfaces of the conductive strips in at least one of the top plane of conductive strips and the bottom plane of conductive strips.

First claim

What is claimed is:

1. A memory device including an array of strings of memory cells, comprising:
a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips;
a plurality of vertical active strips between the plurality of stacks;
charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and the vertical active strips in the plurality of vertical active strips; and
gate dielectric, having a different composition than the charge storage structures, in interface regions at cross-points between and contacting the vertical active strips in the plurality of vertical active strips and side surfaces of the conductive strips in the top plane of conductive strips,
wherein the insulating material separating conductive strips in the stacks of conductive strips contacts vertical active strips in the plurality of vertical active strips, and
wherein conductive strips in at least one of the bottom plane and the top plane have different material than conductive strips in the plurality of intermediate planes.

2. The memory device of claim 1 , comprising silicide formations on top of and in contact with the top plane of conductive strips.

3. The memory device of claim 1 , comprising spacers to isolate the vertical active strips from silicide formations on top of and in contact with the top plane of conductive strips, and silicide formations on top of the vertical active strips.

4. The memory device of claim 1 , wherein the gate dielectric comprises a layer of silicon oxide material and is thinner than the charge storage structures.

5. The memory device of claim 1 , wherein a reference conductor is disposed in a level between the bottom plane of conductive strips and an integrated circuit substrate, and connected to the plurality of vertical active strips.

6. The memory device of claim 5 , wherein the reference conductor includes N+ doped semiconductor material.

7. The memory device of claim 1 , further including charge storage structures between conductive strips within a stack in the stacks of conductive strips and insulating material separating the conductive strips.

8. The memory device of claim 7 , wherein said charge storage structures between conductive strips in the stacks of conductive strips and insulating material separating the conductive strips are in contact with said charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and the vertical active strips in the plurality of vertical active strips.

9. The memory device of claim 1 , further comprising:
said gate dielectric, having a different composition than the charge storage structures, in interface regions at cross-points between the vertical active strips in the plurality of vertical active strips and side surfaces of the conductive strips in both the top plane of conductive strips and the bottom plane of conductive strips.

10. The memory device of claim 1 , wherein the charge storage structures are separated from the gate dielectric.

11. The memory device of claim 1 , wherein the gate dielectric is an oxide of the material of the conductive strips in the bottom plane and in the top plane.

12. A memory device including an array of strings of memory cells, comprising:
a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips;
a plurality of vertical active strips between the plurality of stacks;
charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and the vertical active strips in the plurality of vertical active strips; and
gate dielectric, having a different composition than the charge storage structures, in interface regions at cross-points between and contacting the vertical active strips in the plurality of vertical active strips and side surfaces of the conductive strips in both the top plane of conductive strips and the bottom plane of conductive strips,
wherein conductive strips in at least one of the bottom plane and the top plane have different material than conductive strips in the plurality of intermediate planes.

13. The memory device of claim 12 , wherein the gate dielectric is an oxide of the material of the conductive strips in the bottom plane and in the top plane.

Assignees

• Macronix Int Co Ltd

Inventors

• Lai Erh-Kun

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title