Integrated circuit device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9466611-B2
Application number	US-201514812376-A
Country	US
Kind code	B2
Filing date	Jul 29, 2015
Priority date	Sep 16, 2014
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

An integrated circuit device according to one embodiment includes a plurality of first electrode films stacked spaced from each other, a plurality of second electrode films stacked spaced from each other on the plurality of first electrode films and extending in one direction, a semiconductor pillar penetrating the first electrode films and the second electrode films, a memory film provided between the first electrode films and the semiconductor pillar and capable of storing charge, a gate insulating film provided between the second electrode films and the semiconductor pillar, and a spacer film electrically connecting width-direction edges of the plurality of second electrode films to each other.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a plurality of first electrode films stacked spaced from each other;
a plurality of second electrode films stacked spaced from each other, on the plurality of first electrode films, and extending in one direction;
a semiconductor pillar penetrating the first electrode films and the second electrode films;
a memory film provided between the first electrode films and the semiconductor pillar and capable of storing charge;
a gate insulating film provided between the second electrode films and the semiconductor pillar; and
a spacer film electrically connecting width-direction edges of the plurality of second electrode films to each other.

2. The device according to claim 1 , wherein the spacer film extends along a plane including the one direction and a stacking direction of the plurality of second electrode films.

3. The device according to claim 1 , wherein the spacer film connects respective ones of both width-direction edges of the plurality of second electrode films to each other.

4. The device according to claim 1 , further comprising a via penetrating the plurality of second electrode films and connecting the plurality of second electrode films to each other.

5. The device according to claim 1 , wherein the spacer film contains metal silicide.

6. The device according to claim 1 , wherein the spacer film is conductive and contains silicon.

7. The device according to claim 1 , further comprising another spacer film whose composition is different from a composition of the spacer film.

8. The device according to claim 7 , wherein the another spacer film is insulative.

9. The device according to claim 8 , wherein the another spacer film contains aluminum oxide.

10. The device according to claim 9 , wherein the spacer film is conductive and contains silicon.

Assignees

• Toshiba Kk

Inventors

• Komori Yosuke
• Hyodo Yasuyoshi

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P14/414

  of metal-silicide materials · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/0413 Primary

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title