Semiconductor device having a ferroelectric gate stack

Patent metadata

Field	Value
Publication number	US-11791383-B2
Application number	US-202117387504-A
Country	US
Kind code	B2
Filing date	Jul 28, 2021
Priority date	Jul 28, 2021
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A semiconductor device includes a SiC substrate and a plurality of transistor cells formed in the SiC substrate and electrically connected in parallel to form a transistor. Each transistor cell includes a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the SiC substrate. The gate dielectric stack includes a ferroelectric insulator. The transistor has a specified operating temperature range, and the ferroelectric insulator is doped with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor. A corresponding method of producing the semiconductor device is also described.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a SiC substrate; and
a plurality of transistor cells formed in the SiC substrate and electrically connected in parallel to form a transistor,
wherein each transistor cell of the plurality of transistor cells comprises a gate structure including a gate electrode and a gate dielectric stack separating the gate electrode from the SiC substrate,
wherein the gate dielectric stack comprises a ferroelectric insulator,
wherein the transistor has a specified operating temperature range,
wherein the ferroelectric insulator is doped with a doping material such that the Curie temperature of the ferroelectric insulator is in a range above the specified operating temperature range of the transistor.

2. The semiconductor device of claim 1 , wherein the gate dielectric stack further comprises a first non-ferroelectric insulator.

3. The semiconductor device of claim 2 , wherein the first non-ferroelectric insulator contacts the SiC substrate.

4. The semiconductor device of claim 3 , wherein the first non-ferroelectric insulator comprises silicon dioxide, and wherein an interface region between the silicon dioxide and the SiC substrate contains nitrogen.

5. The semiconductor device of claim 2 , wherein the first non-ferroelectric insulator comprises silicon dioxide, wherein the ferroelectric insulator comprises hafnium oxide, and wherein a combined thickness of the silicon dioxide and the hafnium oxide is in a range of 10 nm to 200 nm.

6. The semiconductor device of claim 2 , wherein the ferroelectric insulator is thicker than the first non-ferroelectric insulator.

7. The semiconductor device of claim 2 , wherein the gate dielectric stack further comprises a second non-ferroelectric insulator, and wherein the ferroelectric insulator is interposed between the first non-ferroelectric insulator and the second non-ferroelectric insulator.

8. The semiconductor device of claim 7 , wherein the first non-ferroelectric insulator contacts the SiC substrate and comprises silicon dioxide, wherein the ferroelectric insulator comprises hafnium oxide, and wherein the second non-ferroelectric insulator comprises silicon dioxide or aluminum oxide or hafnium oxide with a doping level resulting in a Curie temperature below the minimum operation temperature.

9. The semiconductor device of claim 7 , wherein the first non-ferroelectric insulator contacts the SiC substrate, and wherein the second non-ferroelectric insulator is thinner or thicker than the first non-ferroelectric insulator.

10. The semiconductor device of claim 2 , wherein each transistor cell of the plurality of transistor cells further comprises a p-type body region formed in the SiC substrate, and wherein the first non-ferroelectric insulator contacts the p-type body region.

11. The semiconductor device of claim 10 , wherein the p-type body region has a doping concentration in a range of 1E17 cm −3 to 2E18 cm −3 .

12. The semiconductor device of claim 10 , wherein a doping concentration of the p-type body region is a function of a polarization density of the ferroelectric insulator below the Curie temperature, such that the transistor has a threshold voltage that is higher for temperatures above the Curie temperature and lower for temperatures within the specified operating temperature range of the transistor.

13. The semiconductor device of claim 1 , wherein the ferroelectric insulator comprises hafnium oxide, and wherein the doping material has a doping level such that the Curie temperature of the ferroelectric insulator exceeds 200° C.

14. The semiconductor device of claim 1 , wherein the doping material comprises one or more impurity species selected from the group consisting of Al, Si, Gd, Yr, La, Sr, and Zr.

15. The semiconductor device of claim 1 , wherein the gate structure of each transistor cell of the plurality of transistor cells is a trench gate structure disposed in a trench formed in the SiC substrate.

16. The semiconductor device of claim 1 , wherein the transistor has a maximum operating temperature below 200° C., and wherein the Curie temperature of the ferroelectric insulator is in a range of 200° C. to 1500° C.

17. The semiconductor device of claim 1 , wherein the ferroelectric insulator comprises hafnium oxide.

18. The semiconductor device of claim 17 , wherein the doping material comprises one or more impurity species selected from the group consisting of Al, Si, Gd, Yr, La, Sr, and Zr.

19. The semiconductor device of claim 1 , wherein below the Curie temperature, the ferroelectric insulator has a polarization density in a range of 0.5 μC/cm 2 to 4 μC/cm 2 .

20. The semiconductor device of claim 1 , wherein the transistor has a threshold voltage that is higher at temperatures above the Curie temperature and lower at temperatures within the specified operating temperature range of the transistor.

21. The semiconductor device of claim 1 , wherein the ferroelectric insulator comprises two or more layers having different doping levels.

22. The semiconductor device of claim 1 , wherein the ferroelectric insulator comprises two or more different ferroelectric materials.

23. The semiconductor device of claim 22 , wherein the ferroelectric insulator comprises doped HfO 2 and AlScN.

Assignees

• Infineon Technologies Ag

Inventors

• Roy Saurabh
• Aichinger Thomas
• Schulze Hans-Joachim

Classifications

• H10D64/689

  having ferroelectric layers · CPC title

• H10D48/01

  Manufacture or treatment · CPC title

• H10D30/701 Primary

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D12/031

  of IGBTs · CPC title