Negative capacitance field effect transistor with charged dielectric material

Patent metadata

Field	Value
Publication number	US-9978868-B2
Application number	US-201514942005-A
Country	US
Kind code	B2
Filing date	Nov 16, 2015
Priority date	Nov 16, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a substrate; a gate stack over the substrate. The gate stack includes a ferroelectric layer; a first dielectric material layer; and a first conductive layer. One of the first dielectric material layer and the ferroelectric layer is electrically charged to form a charged layer with fixed charge. The semiconductor device further includes source and drain features formed on the substrate and disposed on sides of the gate stack.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a gate stack over the substrate, wherein the gate stack includes:
a ferroelectric layer;
a first dielectric material layer; and
a first conductive layer; and

source and drain features formed on the substrate and disposed on sides of the gate stack, wherein one of the first dielectric material layer and the ferroelectric layer is electrically charged to form a charged layer with a fixed charge such that the semiconductor device is hysteresis-free.

2. The semiconductor device of claim 1 , wherein
the first dielectric material layer is the charged layer and disposed on the substrate;
the ferroelectric layer is disposed on the charged layer; and
the first conductive layer is disposed on the ferroelectric layer.

3. The semiconductor device of claim 2 , further comprising a second dielectric material layer interposed between the ferroelectric layer and the first dielectric material layer.

4. The semiconductor device of claim 3 , further comprising a second conductive layer disposed between the second dielectric material layer and the ferroelectric layer.

5. The semiconductor device of claim 3 , further comprising a second conductive layer disposed between the first dielectric material layer and the second dielectric material layer.

6. The semiconductor device of claim 2 , further comprising a second conductive layer interposed between the ferroelectric layer and the first dielectric material layer.

7. The semiconductor device of claim 6 , wherein the first dielectric material layer is not the charged layer and the ferroelectric layer is the charged layer with fixed charge.

8. The semiconductor device of claim 3 , wherein the ferroelectric layer is the charged layer with fixed charge and the first dielectric layer is not the charged layer.

9. The semiconductor device of claim 1 , wherein
the ferroelectric layer includes a ferroelectric material selected from the group consisting of HfSiOx, HfZrOx, Al2O3, TiO2, LaOx, BaSrTiOx (BST), PbZrxTiyOz (PZT), and a combination thereof.

10. The semiconductor device of claim 1 , wherein the charged layer has a charge density of 5×10 13 cm −2 within 10% variation.

11. The semiconductor structure of claim 1 , further comprising a second gate stack interposed between the substrate and a channel region and a shallow trench isolation (STI) feature disposed below the second gate stack, wherein the channel region is interposed between the gate stack and the second gate stack vertically and disposed between the source and the drain in horizontally.

12. The device of claim 1 , wherein the ferroelectric layer has a thickness between 0.1 μm to 1 μm.

13. The device of claim 1 , wherein the conductive layer includes a metallic material selected from the group consisting of silver, aluminum, copper, tungsten, nickel, alloys, and metal compound.

14. A semiconductor device comprising:
a shallow trench isolation (STI) feature in a substrate
a first gate stack directly on the STI feature;
a channel region disposed on the first gate stack;
a second gate stack disposed on the channel region; and
a source and a drain laterally configured on two sides of the channel region and connected to the channel region, wherein each of the first and second gate stacks includes:
a ferroelectric layer;
a first dielectric material layer; and
a first conductive layer, wherein one of the first dielectric material layer and the ferroelectric layer is electrically charged as a charged layer with fixed charge.

15. The semiconductor device of claim 12 , further comprising a first semiconductor feature and a second semiconductor feature formed on the substrate and contacting the sides of the first and second gate stacks, wherein the first and second semiconductor features are vertically extended from the substrate to a semiconductor top surface being coplanar with a top surface of the second gate stack; and the source and drain are portions of the first and second semiconductor features, respectively.

16. The semiconductor device of claim 15 , wherein the first and second semiconductor features include germanium and the dielectric material layer includes germanium oxide.

17. The semiconductor device of claim 14 , wherein
the first and the second gate stacks are symmetrically configured on bottom surface and top surface of the channel region, respectively;
the STI feature, the first gate stack, the channel region and the second gate stack laterally span a same dimension;
the two sides of the channel region are aligned with corresponding sides of the STI feature, the first gate stack, and the second gate stack; and
the source and drain disposed directly on an active region, continuously extended from the active region, and having sides aligned with the sides of the STI feature, the first gate stack, the channel region and the second gate stack.

18. A semiconductor device comprising:
a gate stack over a substrate, wherein the gate stack includes:
a first dielectric material layer formed over the substrate;
a second dielectric material layer formed over the first dielectric material layer;
a second conductive layer disposed between the first dielectric material layer and the second dielectric material layer;
a ferroelectric layer formed over the second dielectric layer; and
a first conductive layer formed over the ferroelectric layer; and

source and drain features formed on the substrate and disposed on sides of the gate stack, wherein the first dielectric material layer is electrically charged to form a charged layer with a fixed charge and a charge density of 5×10 13 cm −2 within 10% variation.

19. The device of claim 18 , wherein
the ferroelectric layer has a thickness ranging from 0.1 μm to 1 μm; and
the ferroelectric layer includes a ferroelectric material selected from the group consisting of HfSiOx, HfZrOx, Al2O3, TiO2, LaOx, BaSrTiOx (BST), PbZrxTiyOz (PZT), and a combination thereof.

20. The device of claim 18 , wherein the fixed charge is present in the charged layer regardless whether the semiconductor device is biased.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ Nat Taiwan
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lai Der-Chuan
• Pan Samuel C
• Shen Yu-Cheng
• Lee Min-Hung
• Liu Chee-Wee

Classifications

• H01L29/6684

  Electricity · mapped topic

• H01L29/401

  Electricity · mapped topic

• H01L29/516

  Electricity · mapped topic

• H01L29/16

  Electricity · mapped topic

• H01L29/7856

  Electricity · mapped topic