Semiconductor device

Patent metadata

Field	Value
Publication number	US-9871136-B2
Application number	US-201615206319-A
Country	US
Kind code	B2
Filing date	Jul 11, 2016
Priority date	Jun 8, 2016
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
an electrode layer disposed on the substrate; and
a tri-layered gate-control stack sandwiched between the substrate and the electrode layer, the tri-layered gate-control stack comprising:
a ferroelectric (FE) layer disposed on the substrate;
an anti-ferroelectric (AFE) layer sandwiched between the ferroelectric layer and the substrate, the FE layer and the AFE layer comprising different materials, wherein the AFE layer comprises a material selected from the group consisting of lead indium niobate (Pb(InNb)O 3 ), niobium-sodium oxide (NbNaO 3 ), lead zirconate (ZrPbO 3 ), lead lanthanum zirconate titanate (TiZrLaPbO 2 ), lead zirconate titanate (TiZrPbO 3 ), ammonium dihydrogen phosphate (NH 4 H 2 PO 4 , ADP), and ammonium dihydrogen arsenate (NH 4 H 2 AsO 4 , ADA); and
a mid-gap metal layer sandwiched between the ferroelectric layer and the AFE layer.

2. The semiconductor device according to claim 1 , wherein the electrode layer comprises at least a work function metal layer for a p-typed semiconductor device or for an n-typed semiconductor device.

3. The semiconductor device according to claim 1 , further comprising an oxide liner layer sandwiched between the AFE layer of the tri-layered gate-control stack and the substrate.

4. The semiconductor device according to claim 1 , wherein the ferroelectric layer comprises a material selected from the group consisting of lead zirconate titanate ( P bZrTiO 3 , PZT), lead lanthanum zirconate titanate (PbLa(TiZr)O 3 , PLZT), strontium bismuth tantalate (SrBiTa 2 O 9 , SBT), bismuth lanthanum titanate ((BiLa) 4 Ti 3 O 12 , BLT), and barium strontium titanate (BaSrTiO 3 , BST).

5. The semiconductor device according to claim 1 , wherein the mid-gap metal layer comprises metal nitride.

6. The semiconductor device according to claim 1 , further comprising a bottom barrier layer and an etch stop layer sandwiched between the tri-layered gate-control stack and the electrode layer.

7. The semiconductor device according to claim 1 , wherein the tri-layered gate-control stack comprises a U shape.

8. A semiconductor device comprising:
a substrate;
an electrode layer disposed on the substrate; and
a tri-layered gate-control stack sandwiched between the substrate and the electrode layer, the tri-layered gate-control stack comprising:
an amorphous ferroelectric (FE) dielectric layer;
a mid-gap metal layer disposed between the amorphous ferroelectric dielectric layer and the substrate, the mid-gap metal layer directly contacting the amorphous ferroelectric dielectric layer; and
a polycrystalline dielectric layer,
wherein the amorphous ferroelectric dielectric layer and the polycrystalline dielectric layer both comprise hafnium oxide materials.

9. The semiconductor device according to claim 8 , wherein the polycrystalline dielectric layer is sandwiched between the mid-gap metal layer and the substrate.

10. The semiconductor device according to claim 8 , wherein the electrode layer comprise at least a work function metal layer for a p-typed semiconductor device or for an n-typed semiconductor device.

11. A semiconductor device comprising:
a substrate;
an electrode layer disposed on the substrate; and
a tri-layered gate-control stack sandwiched between the substrate and the electrode layer, the tri-layered gate-control stack comprising:
a ferroelectric (FE) layer disposed on the substrate, wherein the ferroelectric layer comprises a material selected from the group consisting of lead zirconate titanate ( P bZrTiO 3 , PZT), lead lanthanum zirconate titanate (PbLa(TiZr)O 3 , PLZT), strontium bismuth tantalate (SrBiTa 2 O 9 , SBT), bismuth lanthanum titanate ((BiLa) 4 Ti 3 O 12 , BLT), and barium strontium titanate (BaSrTiO 3 , BST);
an anti-ferroelectric (AFE) layer sandwiched between the ferroelectric layer and the substrate, the FE layer and the AFE layer comprising different materials; and

a mid-gap metal layer sandwiched between the ferroelectric layer and the AFE layer.

12. The semiconductor device according to claim 11 , wherein the electrode layer comprises at least a work function metal layer for a p-typed semiconductor device or for an n-typed semiconductor device.

13. The semiconductor device according to claim 11 , further comprising an oxide liner layer sandwiched between the AFE layer of the tri-layered gate-control stack and the substrate.

14. The semiconductor device according to claim 11 , wherein the mid-gap metal layer comprises metal nitride.

15. The semiconductor device according to claim 11 , wherein the AFE layer comprises a material selected from the group consisting of lead indium niobate (Pb(InNb)O 3 ), niobium-sodium oxide (NbNaO 3 ), lead zirconate (ZrPbO 3 ), lead lanthanum zirconate titanate (TiZrLaPbO 3 ), lead zirconate titanate (TiZrPbO 3 ), ammonium dihydrogen phosphate (NH 4 H 2 PO 4 , ADP), and ammonium dihydrogen arsenate (NH 4 H 2 AsO 4 , ADA).

16. The semiconductor device according to claim 11 , further comprising a bottom barrier layer and an etch stop layer sandwiched between the tri-layered gate-control stack and the electrode layer.

17. The semiconductor device according to claim 11 , wherein the tri-layered gate-control stack comprises a U shape.

Assignees

• United Microelectronics Corp

Inventors

• Chen Shih-Cheng
• Wen Tsai-Yu
• Ye Shan
• Lu Tsuo-Wen

Classifications

• H01L29/4966

  Electricity · mapped topic

• H01L29/516

  Electricity · mapped topic

• H01L29/6684

  Electricity · mapped topic

• H01L29/517

  Electricity · mapped topic

• H01L29/78391 Primary

  Electricity · mapped topic