Semiconductor package with thick under-bump terminal

Patent metadata

Field	Value
Publication number	US-11791295-B2
Application number	US-202016795733-A
Country	US
Kind code	B2
Filing date	Feb 20, 2020
Priority date	Jul 22, 2019
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

Disclosed is a semiconductor package comprising a redistribution substrate, and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate includes an under-bump pattern, a lower dielectric layer that covers a sidewall of the under-bump pattern, and a first redistribution pattern on the lower dielectric layer. The first redistribution pattern includes a first line part. A width at a top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern. A thickness of the under-bump pattern is greater than a thickness of the first line part.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a redistribution substrate; and
a semiconductor chip on a top surface of the redistribution substrate,
wherein the redistribution substrate includes:
an under-bump pattern;
a lower dielectric layer that covers a sidewall of the under-bump pattern; and
a first redistribution pattern on the lower dielectric layer,

wherein the first redistribution pattern includes:
a first conductive layer on a top surface of the lower dielectric layer and including a first tapered via part and a first line part, the first line part extending in a horizontal direction and connected to the first tapered via part; and
a first seed layer between the top surface of the lower dielectric layer and the first conductive layer, the first seed layer covering a bottom surface and side surfaces of the first tapered via part and a bottom surface of the first line part,

wherein a bottom surface of the seed layer covering the first tapered via part directly contacts a top surface of the under-bump pattern,
wherein the top surface of the under-bump pattern is at a vertical level the same as or less than that of the top surface of the lower dielectric layer,
wherein a width at the top surface of the under-bump pattern is greater than a width at a bottom surface of the under-bump pattern,
wherein the under-bump pattern narrows from the top surface of the under-bump pattern to the bottom surface of the under-bump pattern to form a tapered shape having a side surface that extends linearly from the top surface of the under-bump pattern to the bottom surface of the under-bump pattern, and
wherein a thickness of the under-bump pattern is greater than a thickness of the first line part.

2. The semiconductor package of claim 1 , wherein a width of the first tapered via part is less than the width at the top surface of the under-bump pattern.

3. The semiconductor package of claim 1 , wherein the thickness of the under-bump pattern is 2.5 to 10 times the thickness of the first line part.

4. The semiconductor package of claim 1 ,
wherein the first line part includes a plurality of first line parts that are spaced apart from each other, and
wherein a maximum interval between a bottom surface of the lower dielectric layer and bottom surfaces of the first line parts is 100% to 130% of a minimum interval between the bottom surface of the lower dielectric layer and the bottom surfaces of the first line parts.

5. The semiconductor package of claim 1 , further comprising:
an upper dielectric layer on the lower dielectric layer; and
a second redistribution pattern on a top surface of the upper dielectric layer, the second redistribution pattern including a second line part,
wherein the thickness of the under-bump pattern is greater than a thickness of the second line part.

6. The semiconductor package of claim 1 , further comprising an external terminal on the bottom surface of the under-bump pattern.

7. The semiconductor package of claim 6 , further comprising:
a lower under-bump pattern between the under-bump pattern and the external terminal; and
a seed pattern between the lower under-bump pattern and the under-bump pattern,
wherein the lower under-bump pattern includes a material different from a material of the under-bump pattern.

8. The semiconductor package of claim 1 , further comprising:
a connection substrate on the redistribution substrate, the connection substrate including a plurality of base layers and a conductive structure,
wherein the connection substrate has a hole, and
wherein the semiconductor chip is disposed in the hole.

9. The semiconductor package of claim 1 , further comprising:
a conductive structure on the top surface of the redistribution substrate, the conductive structure being spaced apart from the semiconductor chip; and
a molding layer on the top surface of the redistribution substrate, the molding layer encapsulating the semiconductor chip and a sidewall of the conductive structure.

10. The semiconductor package of claim 1 , further comprising:
a solder terminal,
wherein a bottom surface of the under-bump pattern is coplanar with a bottom surface of the dielectric layer, and
wherein the solder terminal contacts the bottom surface of the under-bump pattern.

11. A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate; and
a solder terminal on a bottom surface of the redistribution substrate,
wherein the redistribution substrate includes:
an under-bump pattern;
a dielectric layer that covers a sidewall of the under-bump pattern; and
a redistribution pattern on the under-bump pattern and on the dielectric layer, the redistribution pattern being coupled to the under-bump pattern,

wherein the solder terminal is on a bottom surface of the under-bump pattern,
wherein the redistribution pattern includes:
a conductive layer including a tapered via part and a line part, the line part extending in a horizontal direction and connected to the tapered via part; and
a seed layer covering a bottom surface and side surfaces of the tapered via part and a bottom surface of the line part, the seed layer being spaced apart from a top surface of the line part,

wherein the sidewall of the under-bump pattern is in direct contact with the dielectric layer,
wherein a top surface of the under-bump pattern is at a vertical level the same as or less than that of a top surface of the dielectric layer,
wherein a bottom surface of the seed layer covering the tapered via part directly contacts the top surface of the under-bump pattern,
wherein the seed layer includes different material from the under-bump pattern,
wherein an angle between the sidewall and a top surface of the under-bump pattern is an acute angle, and
wherein an angle between the sidewall and the bottom surface of the under-bump pattern is in a range from 105° to 135°.

12. The semiconductor package of claim 11 ,
wherein the sidewall extends linearly from the top surface of the under-bump pattern to the bottom surface of the under-bump pattern,
wherein the under-bump pattern narrows from the top surface of the under-bump pattern to the bottom surface of the under-bump pattern to form a tapered shape, and
wherein the dielectric layer exposes the bottom surface of the under-bump pattern.

13. The semiconductor package of claim 12 , wherein the bottom surface of the under-bump pattern is coplanar with a bottom surface of the dielectric layer.

14. The semiconductor package of claim 11 , wherein a width of the tapered via part is less than a width of the under-bump pattern.

15. The semiconductor package of claim 11 ,
wherein a bottom surface of the under-bump pattern is coplanar with a bottom surface of the dielectric layer, and
wherein the solder terminal contacts the bottom surface of the under-bump pattern.

16. A semiconductor package, comprising:
a redistribution substrate;
a semiconductor chip on a top surface of the redistribution substrate; and
a solder terminal on a bottom surface of the redistribution substrate,
wherein the redistribution substrate includes:
a conductive terminal pad;
a lower under-bump pattern provided on a bottom surface of the conductive terminal pad and including different material from the conductive terminal pad;
a lower dielectric layer that covers a sidewall of the conductive terminal pad;
a line pattern on the lower dielectric layer; and
a tapered via between the conductive terminal pad and the line pattern, the tapered v

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Gwangjae
• Kim Dongkyu
• Park Jung-Ho
• Jang Yeonho

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title