Semiconductor package with improved redistribution layer design and fabricating method thereof

Patent metadata

Field	Value
Publication number	US-9293403-B2
Application number	US-201313955422-A
Country	US
Kind code	B2
Filing date	Jul 31, 2013
Priority date	Aug 30, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A semiconductor package with improved redistribution layer design and fabricating method thereof are disclosed and may include a semiconductor die comprising bond pads, a first redistribution layer (RDL) formed on the semiconductor die. The first RDL has a first end coupled to a bond pad and a second end coupled to a solder bump via under bump metal layers. A second RDL is formed in a same plane of the semiconductor die as the first RDL and is electrically isolated from the first RDL. A first end of the second RDL may be coupled to a bond pad and the second RDL may pass underneath, but be electrically isolated from, the solder bump. A passivation layer may be formed on the first and second RDLs exposing the second end of the first RDL. The under bump metal layers may be formed on the second end of the first RDL exposed by the passivation layer.

First claim

What is claimed is:

1. A semiconductor package comprising:
a semiconductor die comprising a plurality of bond pads;
a first redistribution layer (RDL) on the semiconductor die;
a second RDL in a same plane of the semiconductor package as at least a portion of the first RDL, the second RDL being electrically isolated from the first RDL; and
an interconnection structure over at least the portion of the first RDL and a portion of the second RDL;
wherein:
the second RDL passes underneath a center of, but is electrically isolated from, the interconnection structure; and
the portion of the first RDL comprises a majority of an area under the interconnection structure.

2. The package according to claim 1 , wherein a passivation layer is formed on the first RDL and the second RDL exposing a second end of the first RDL.

3. The package according to claim 2 , wherein one or more under bump metal layers is on the second end of the first RDL exposed by the passivation layer.

4. The package according to claim 2 , wherein the passivation layer electrically isolates the first RDL and the solder bump from the second RDL.

5. The package according to claim 3 , wherein the passivation layer is between the one or more under bump metal layers and the second RDL.

6. The package according to claim 2 , wherein the passivation layer is formed between the first RDL and the second RDL.

7. The package according to claim 2 , wherein the passivation layer comprises one or more of: polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide-triazine (BT), phenolic resin, epoxy, silicone, oxide (SiO 2 ), and nitride (Si 3 N 4 ).

8. The package according to claim 1 , wherein a second end of the second RDL is coupled to a second interconnection structure via one or more under bump metal layers.

9. The package according to claim 1 , wherein a third RDL passes underneath, but is electrically isolated from, the interconnection structure.

10. The package according to claim 1 , wherein the first RDL and the second RDL are formed on one or more seed layers.

11. The package according to claim 1 , wherein:
a first end of the first RDL is coupled to at least one of said plurality of bond pads and a second end of the first RDL is coupled to the interconnection structure via one or more under bump metal layers;
a first end of the second RDL is coupled to at least one of said plurality of bond pads; and
the interconnection structure comprises a solder bump.

12. A method for forming a semiconductor package, the method comprising:
providing a semiconductor die comprising a plurality of bond pads;
forming a first redistribution layer (RDL) on the semiconductor die, the first RDL having a first end coupled to a bond pad and a second end coupled to a solder bump via one or more under bump metal layers;
forming a second RDL in a same plane of the semiconductor package as at least a portion of the first RDL, the second RDL being electrically isolated from the first RDL; and
coupling a first end of the second RDL to at least one of said plurality of bond pads;
wherein:
the second RDL passes underneath a center of, but is electrically isolated from, the solder bump coupled to the second end of the first RDL; and
the portion of the first RDL comprises a majority of an area under the solder bump.

13. The method according to claim 12 , comprising forming a passivation layer on the first RDL and the second RDL exposing the second end of the first RDL.

14. The method according to claim 13 , comprising forming the one or more under bump metal layers on the second end of the first RDL exposed by the passivation layer.

15. The method according to claim 13 , wherein the passivation layer electrically isolates the first RDL and the solder bump from the second RDL.

16. The method according to claim 13 , comprising forming the passivation layer between the under bump metal and the second RDL.

17. The method according to claim 13 , comprising forming the passivation layer between the first RDL and the second RDL.

18. The method according to claim 13 , wherein the passivation layer comprises one or more of: polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide-triazine (BT), phenolic resin, epoxy, silicone, oxide (SiO 2 ), and nitride (Si 3 N 4 ).

19. The method according to claim 12 , comprising coupling a second end of the second RDL to a second solder bump via one or more under bump metal layers.

20. The method according to claim 12 , wherein a third RDL passes underneath, but is electrically isolated from, the solder bump coupled to the second end of the first RDL.

21. A semiconductor package comprising:
a semiconductor die comprising a plurality of bond pads;
a first redistribution layer (RDL) over the semiconductor die;
a second RDL in a same plane of the semiconductor package as at least a portion of the first RDL and electrically isolated from the first RDL; and
an interconnection structure over at least the portion of the first RDL and a portion of the second RDL;
wherein:
the portion of the second RDL passes underneath, but is electrically isolated from, the interconnection structure; and
the portion of the first RDL comprises a majority of an area under the interconnection structure.

22. The package according to claim 21 , wherein:
a first end of the first RDL is coupled to at least one of said plurality of bond pads and a second end of the first RDL is coupled to the interconnection structure via one or more under bump metal layers;
a first end of the second RDL is coupled to at least one of said plurality of bond pads; and
the interconnection structure comprises a solder bump.

Assignees

• Amkor Technology Inc

Inventors

• Park No Sun
• Ryu Ji Yeon
• Jung Go Woon

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title

• H10W72/01955

  by using masks · CPC title

• H10W72/981

  Auxiliary members, e.g. spacers · CPC title