Systems and methods for designing integrated circuits

Patent metadata

Field	Value
Publication number	US-11790141-B2
Application number	US-202117336916-A
Country	US
Kind code	B2
Filing date	Jun 2, 2021
Priority date	Sep 10, 2018
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.

First claim

What is claimed is:

1. A method of making an integrated circuit, the method comprising:
for each pair of connected logic stages possible for use in the integrated circuit, determining a static noise margin (SNM) for the pair of connected logic stages with a metallic carbon nanotube (m-CNT), the SNM representing an immunity to noise of the pair of logic stages when made with the m-CNT and accounting for a likelihood that either or both logic gates of the pair of connected logic gates include a m-CNT; and
making the integrated circuit with only those pairs of connected logic stages having an SNM above a threshold SNM despite the possible presence of the m-CNT in each pair of those pairs of connected logic gates.

2. The method of claim 1 , wherein determining the SNM for each pair of connected logic stages comprises determining all possible combinations of m-CNTs in the pair of connected logic stages.

3. The method of claim 1 , further comprising:
determining a probability that all noise margin constraints are satisfied using only those pairs of connected logic stages having an SNM above the threshold SNM; and
adjusting the threshold SNM based on the probability that all noise margin constraints are satisfied using only those pairs of connected logic stages having an SNM above the threshold SNM.

4. The method of claim 1 , further comprising:
storing models of SNMs for the pairs of connected logic states possible for use in the integrated circuit in a library; and
designing the integrated circuit with an electronic design automation tool linked to the library.

5. The method of claim 1 , wherein the integrated circuit has a semiconductor-carbon nanotube (s-CNT) purity of at most 99.99%.

6. The method of claim 1 , wherein the integrated circuit includes at least one thousand connected logic stages.

7. The method of claim 1 , further comprising, prior to making the integrated circuit:
generating a circuit design for the integrated circuit using only those pairs of connected logic stages having an SNM above a threshold SNM; and
determining a performance parameter for the integrated circuit based on the circuit design.

8. A method of making an integrated circuit, the method comprising:
for each pair of connected logic stages possible for use in the integrated circuit, determining a static noise margin (SNM) for the pair of connected logic stages with a metallic carbon nanotube (m-CNT), the SNM representing an immunity to noise of the pair of logic stages when made with the m-CNT;
selecting a circuit design for the integrated circuit based on only those pairs of connected logic stages having an SNM above a threshold SNM and determining a performance parameter for the integrated circuit based on the circuit design, wherein the selected circuit design is one of a set of circuit designs, wherein the performance parameter is at least one of power consumption, switching delay, or surface area, and wherein the selected circuit design (a) has a 99% likelihood that it meets a maximum noise criterion and (b) has the lowest value among the set of circuit designs for the at least one of the power consumption, switching delay, or surface area; and
making the integrated circuit with the circuit design, such that the integrated circuit includes only those pairs of connected logic stages having an SNM above a threshold SNM.

9. The integrated circuit made according to the method of claim 1 .

10. A method of making an integrated circuit, the method comprising:
for each pair of connected logic stages possible for use in the integrated circuit, determining a static noise margin (SNM) for the pair of connected logic stages based on a probability of having a metallic carbon nanotube field-effect transistor in a first pair of connected logic stages, the SNM representing an immunity to noise of the pair of connected logic stages; and
selecting pairs of connected logic stages for use in the integrated circuit based on the SNMs for the pairs of connected logic stages and a desired probability of satisfying all noise margin constraints for the integrated circuit.

11. The method of claim 10 , further comprising:
determining the SNM for a first pair of connected logic stages based on a device-to-device variability of transistors in the first pair of connected logic stages.

12. The method of claim 10 , further comprising manufacturing the integrated circuit based on the selected pairs of connected logic stages.

13. The method of claim 12 , wherein the manufacturing does not include removal of any metallic-carbon nanotubes (m-CNTs).

14. A method of making an integrated circuit, the method comprising:
for each pair of connected logic stages possible for use in the integrated circuit, determining a static noise margin (SNM) for the pair of connected logic stages, the SNM representing an immunity to noise of the pair of connected logic stages; and
selecting pairs of connected logic stages for use in the integrated circuit based on the SNMs for the pairs of connected logic stages and a desired probability of satisfying all noise margin constraints for the integrated circuit,
wherein the SNM further represents that at least one logic stage of that pair of logic stages comprises a metallic carbon nanotube (m-CNT).

15. The method of claim 10 , wherein selecting the pairs of connected logic stages comprises weighting each pair of connected logic stages based on its corresponding SNM.

16. The method of claim 10 , further comprising selecting at least one combination of two or more pairs of connected logic stages, wherein the at least one combination meets the desired probability of satisfying all noise margin constraints for the integrated circuit.

17. The method of claim 10 , wherein selecting the pairs of connected logic stages is further based on one or more of:
satisfying timing constraints for the integrated circuit;
satisfying power consumption constraints for the integrated circuit; or
satisfying area constraints for the integrated circuit.

Assignees

• Massachusetts Inst Technology

Inventors

• Hills Gage Krieger
• Shulaker Max

Classifications

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/337

  Design optimisation · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title