Automatic compilation method and framework for generating a layout of integrated memory-compute circuit
US-2024403527-A1 · Dec 5, 2024 · US
Design optimisation
Design optimisation · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F30/337 |
| Official title | Design optimisation |
| Display label | Design optimisation |
| Total patents | 747 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 15 |
| 2016 | 21 |
| 2017 | 21 |
| 2018 | 25 |
| 2019 | 37 |
| 2020 | 75 |
| 2021 | 95 |
| 2022 | 122 |
| 2023 | 114 |
| 2024 | 94 |
| 2025 | 100 |
| 2026 | 28 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Machine-learning design enablement platform
US-2018268096-A1 · Sep 20, 2018 · US
Graph based dynamic timing and activity analysis
US-2018121585-A1 · May 3, 2018 · US
Atomic scale grid for modeling semiconductor structures and fabrication processes
US-9852242-B2 · Dec 26, 2017 · US
Lithography system, simulation apparatus, and pattern forming method
US-2017363962-A1 · Dec 21, 2017 · US
Apparatus and methods for leakage current reduction in integrated circuits
US-2017353187-A1 · Dec 7, 2017 · US
Optical proximity correction for directed-self-assembly guiding patterns
US-9836556-B2 · Dec 5, 2017 · US
Method for Eliminating False Paths of a Circuit Unit To Be Implemented Using a System
US-2017344696-A1 · Nov 30, 2017 · US
System and Method for Optimization of Digital Circuits with Timing and Behavior Co-Designed by Introduction and Exploitation of False Paths
US-2017337319-A1 · Nov 23, 2017 · US
Reciprocal quantum logic (rql) circuit simulation system
US-2017329883-A1 · Nov 16, 2017 · US
Timing optimization driven by statistical sensitivites
US-9767239-B1 · Sep 19, 2017 · US
Reciprocal quantum logic (RQL) circuit simulation system
US-9767238-B2 · Sep 19, 2017 · US
Integrated Circuit System With Memory Support And Method Of Manufacture Thereof
US-2017236870-A1 · Aug 17, 2017 · US
Apparatus and methods for leakage current reduction in integrated circuits
US-9698780-B2 · Jul 4, 2017 · US
Post-routing structural netlist optimization for circuit designs
US-9646126-B1 · May 9, 2017 · US
Method and apparatus for master-clone optimization during circuit analysis
US-9639644-B1 · May 2, 2017 · US
Network logic synthesis
US-2017116354-A1 · Apr 27, 2017 · US
Condition analysis
US-2017083637-A1 · Mar 23, 2017 · US
Block-level code coverage in simulation of circuit designs
US-9600613-B1 · Mar 21, 2017 · US
Synthesis Tuning System for VLSI Design Optimization
US-2017076018-A1 · Mar 16, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F30/337?
- CPC G06F30/337 is the Cooperative Patent Classification code for “Design optimisation.”
- How many patents are filed under CPC G06F30/337 (Design optimisation)?
- Our database includes 747 publications tagged with this CPC code.
- Is patent activity under CPC G06F30/337 growing?
- Publication counts under this code: 94 in 2024 vs 100 in 2025 (latest complete years).