Logic Elements Comprising Carbon Nanotube Field Effect Transistor (CNTFET) Devices and Methods of Making Same

US2017005140A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017005140-A1
Application numberUS-201615160301-A
CountryUS
Kind codeA1
Filing dateMay 20, 2016
Priority dateFeb 22, 2010
Publication dateJan 5, 2017
Grant date

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.

First claim

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1 - 20 . (canceled) 21 . A nanotube based transistor device, comprising: a multi-layer nanotube fabric comprising multiple nanotube fabric layers, each of said nanotube fabric layers comprising a plurality of nanotube elements; a first conductive element formed over a first region of said multi-layer nanotube fabric; a second conductive element formed over a second region of said multi-layer nanotube fabric; an insulating element formed over a third region of said multi-layer nanotube fabric, said third region disposed between said first region and said second region; a third conductive element formed over said insulating element; wherein said first conductive element, second conductive element, and third conductive element are separated from one another; and wherein said nanotube fabric layers of said multi-layer nanotube fabric include an ordered nanotube fabric layer. 22 . The nanotube based transistor device of claim 21 , wherein said multi-layer nanotube fabric comprises said ordered nanotube fabric layer formed on a surface of an unordered nanotube fabric layer. 23 . The nanotube based transistor device of claim 21 , wherein said ordered nanotube layer is formed by applying a directional force to an unordered layer of nanotubes. 24 . The nanotube based transistor device of claim 21 , wherein a first nanotube fabric layer of said multi-layer nanotube fabric and a second nanotube fabric layer of said multi-layer nanotube fabric are ordered nanotube fabric layers. 25 . The nanotube based transistor device of claim 21 , wherein a nanotube density of said multi-layer nanotube fabric is at least 80 nanotubes per micrometer. 26 . The nanotube based transistor device of claim 21 , wherein at least some of said nanotubes within said multi-layer nanotube fabric are coated with a dielectric material. 27 . The nanotube based transistor device of claim 21 , wherein said nanotube elements of said multi-layer nanotube fabric have diameters ranging from 0.7 nm to 2.0 nm. 28 . The nanotube based transistor device of claim 21 , wherein said first region of said multi-layer nanotube fabric defines a source region and said first conductive element defines a source conductor. 29 . The nanotube based transistor device of claim 21 , wherein said second region of said multi-layer nanotube fabric defines a drain region and said second conductive element defines a drain conductor. 30 . The nanotube based transistor device of claim 21 , wherein said third conductive element defines a gate conductor, said third region of said multi-layer nanotube fabric defines a channel region, and said insulating element defines a gate insulator element between said gate conductor and said channel region. 31 . The nanotube based transistor device of claim 21 , wherein said insulating element has a thickness ranging from 1 nm to 25 nm. 32 . The nanotube based transistor device of claim 21 , wherein said insulating element is formed from at least one material selected from the list consisting of SiO2, TaO 5 , SiN, Al 2 O 3 , BeO, Y 2 O 2 , ONO, H f O 2 /SiO 2 , and Y 2 O 2 /SiO 2 . 33 . The nanotube based transistor device of claim 21 , wherein said first conductive element, said second conductive element, and said third conductive element conductor are formed from at least one material selected from the list consisting of Al, Au, W, Cu, Co, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, Sc, Y, C, B, P, K, Si, Ge, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TiC, TaN, CoSi x , and TiSi x . 34 . The nanotube based transistor device of claim 21 , wherein said third region of said multi-layer nanotube fabric forms a conductive pathway between said first region and said second region responsive to an electrical bias applied to said third conductive element. 35 . The nanotube based transistor device of claim 21 , wherein said nanotube elements are substantially all semiconducting carbon nanotubes. 36 . The nanotube based transistor device of claim 21 , wherein said nanotube based transistor device is formed within wiring layers of an integrated circuit, and wherein said wiring layers are separated by insulating regions. 37 . The nanotube based transistor device of claim 36 , wherein said multiple wiring layers comprise at least one material selected from the list consisting of Al, Au, W, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, Sc, Y, C, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSi x , and TiSi x . 38 . The nanotube based transistor device of claim 36 , wherein said multiple wiring layers comprise nanotube fabric layers. 39 . The nanotube based transistor device of claim 21 , wherein said multi-layer nanotube fabric comprises donor atoms provided by ion implantation. 40 . The nanotube based transistor device of claim 39 , wherein said donor atoms are selected from the list consisting of potassium, phosphorous, arsenic, scandium, yttrium, and hydrogen. 41 . The nanotube based transistor device of claim 21 , wherein said multi-layer nanotube fabric comprises acceptor atoms provided by ion implantation. 42 . The nanotube based transistor device of claim 41 , where said acceptor atoms are selected from the list consisting of oxygen and boron. 43 . The nanotube based transistor device of claim 21 , wherein said nanotube based transistor device is formed between wiring layers of an integrated circuit, and wherein said wiring layers are separated by insulating regions. 44 . The nanotube based transistor device of claim 21 , comprising an insulating layer, wherein said multi-layer nanotube fabric is disposed on said insulating layer. 45 . The nanotube based transistor device of claim 21 , comprising a substrate, wherein said multi-layer nanotube fabric is positioned separated from said substrate. 46 . The nanotube based transistor device of claim 45 , wherein said substrate is an insulating substrate. 47 . The nanotube based transistor device of claim 21 , comprising a layer of organic semiconducting material, wherein said multi-layer nanotube fabric is disposed on said layer organic semiconducting material. 48 . The nanotube based transistor device of claim 47 , wherein said layer of organic semiconducting material is formed from a material selected from the list consisting of polyfluorene, polythiophenes, polyacetylene, polypyrrole, polyaniline, p-phenylene sulfide, and p-phenylene vinylene. 49 . The nanotube based transistor device of claim 21 , comprising a plastic film, wherein said multi-layer nanotube fabric is disposed on said plastic film. 50 . The nanotube based transistor device of claim 49 , wherein said plastic film is formed from a material selected from the list consisting of polyethylene terephthalate, polymethylmethacrylate, polyamides, polysulfones, and polycyclic olefins. 51 . The nanotube based transistor device of claim 21 , comprising a substrate, wherein said multi-layer nanotube fabric is in contact with a top surface of said substrate. 52 . A method of making a nanotube based transistor device, comprising: depositing multiple nanotube fabric layers to form a multi-layer nanotube fabric, each of said nanotube fabric layers comprising a plurality of nanotube elements; applying a directional force over to least one nanotube fabr

Assignees

Inventors

Classifications

  • Carbon, e.g. diamond-like carbon · CPC title

  • B82Y10/00Primary

    Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

  • Circuit design · CPC title

  • Carbon nanotubes, CNTs · CPC title

  • characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

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What does patent US2017005140A1 cover?
Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circu…
Who is the assignee on this patent?
Nantero Inc
What technology area does this patent fall under?
Primary CPC classification B82Y10/00. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Thu Jan 05 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).