Method for forming source/drain contacts
US-2024379814-A1 · Nov 14, 2024 · US
US8946007B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8946007-B2 |
| Application number | US-201313762044-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 7, 2013 |
| Priority date | May 10, 2012 |
| Publication date | Feb 3, 2015 |
| Grant date | Feb 3, 2015 |
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After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. The removal of the bottom semiconductor layer exposes a horizontal surface of the buried insulator layer present between source and drain regions on which a conductive material layer is formed as a back gate electrode.
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a semiconductor structure comprising: forming a gate stack comprising a gate dielectric, a gate electrode, and a gate cap dielectric on a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, said SOI substrate further comprising a bottom semiconductor layer having a first semiconductor material and a buried insulator layer; forming a source trench and a drain trench through said top semiconductor layer, said bu…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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