Inverted thin channel mosfet with self-aligned expanded source/drain

US8946007B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8946007-B2
Application numberUS-201313762044-A
CountryUS
Kind codeB2
Filing dateFeb 7, 2013
Priority dateMay 10, 2012
Publication dateFeb 3, 2015
Grant dateFeb 3, 2015

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  5. First independent claim

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Abstract

Official abstract text for this publication.

After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. The removal of the bottom semiconductor layer exposes a horizontal surface of the buried insulator layer present between source and drain regions on which a conductive material layer is formed as a back gate electrode.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a semiconductor structure comprising: forming a gate stack comprising a gate dielectric, a gate electrode, and a gate cap dielectric on a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, said SOI substrate further comprising a bottom semiconductor layer having a first semiconductor material and a buried insulator layer; forming a source trench and a drain trench through said top semiconductor layer, said bu…

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What does patent US8946007B2 cover?
After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10D62/021. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).