Three dimensional circuit systems and methods having memory hierarchies

Patent metadata

Field	Value
Publication number	US-11789641-B2
Application number	US-202117349592-A
Country	US
Kind code	B2
Filing date	Jun 16, 2021
Priority date	Jun 16, 2021
Publication date	Oct 17, 2023
Grant date	Oct 17, 2023

Abstract

A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

First claim

What is claimed is:

1. A circuit system comprising:
a first integrated circuit die comprising a core logic region, wherein the core logic region comprises first memory circuits and logic circuits;
a second integrated circuit die comprising second memory circuits, wherein the first and second integrated circuit dies are coupled together in a vertically stacked configuration through die-to-die connections; and
a third integrated circuit die comprising third memory circuits, wherein the third integrated circuit die is coupled to the first integrated circuit die and resides in a plane of the first integrated circuit die that is perpendicular to the die-to-die connections, wherein the logic circuits are coupled to access the first, second, and third memory circuits, wherein the third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits, and wherein the second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

2. The circuit system of claim 1 , wherein the core logic region further comprises digital signal processing circuits that are coupled to access the first, second, and third memory circuits, and wherein the first integrated circuit die further comprises input/output circuits that couple the logic circuits, the first memory circuits, and the digital signal processing circuits to the second memory circuits through the die-to-die connections that are perpendicular to the plane of the first integrated circuit die.

3. The circuit system of claim 1 further comprising:
a fourth integrated circuit die comprising fourth memory circuits and additional logic circuits, wherein the first memory circuits have a larger memory capacity and a smaller memory access bandwidth than the fourth memory circuits;
a fifth integrated circuit die comprising fifth memory circuits, wherein the second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the fifth memory circuits, the fourth and fifth integrated circuit dies are coupled together in a vertically stacked configuration; and
a sixth integrated circuit die comprising sixth memory circuits, wherein the third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the sixth memory circuits, wherein the sixth integrated circuit die is coupled to the fourth integrated circuit die and resides in a plane of the fourth integrated circuit die, and wherein the additional logic circuits are coupled to access the fourth, fifth, and sixth memory circuits.

4. The circuit system of claim 1 , wherein the logic circuits are arranged in first sectors, wherein the second memory circuits are arranged in second sectors, and wherein each of the first sectors is coupled to one of the second sectors through one of the die-to-die connections that is coupled to the first and second integrated circuit dies.

5. The circuit system of claim 1 , wherein each of the second memory circuits comprises first level memories and a second level memory, wherein the core logic region further comprises memory direct access circuits, and wherein each of the memory direct access circuits has access to one of the first level memories and a partition of the second level memory in one of the second memory circuits.

6. The circuit system of claim 5 , wherein the second integrated circuit die further comprises memory controller prefetch engine circuits, wherein each of the memory controller prefetch engine circuits is coupled to one of the second memory circuits, and wherein each of the memory controller prefetch engine circuits pre-fetches data stored in one of the first level memories and the second level memory in one of the second memory circuits.

7. The circuit system of claim 1 , wherein the second memory circuits are arranged in sectors, wherein the second integrated circuit die further comprises a network-on-chip and bridge circuits coupled to the network-on-chip, wherein each of the bridge circuits is coupled to at least one of the second memory circuits in one of the sectors, and wherein the network-on-chip and the bridge circuits are configured to transfer data between the sectors containing the second memory circuits.

8. The circuit system of claim 7 , wherein the network-on-chip is coupled to the third memory circuits through the die-to-die connections that are perpendicular to the plane of the first integrated circuit die.

9. The circuit system of claim 1 , wherein the first memory circuits are coupled to the second memory circuits through interconnections in the first integrated circuit die and through the die-to-die connections that are perpendicular to the plane of the first integrated circuit die.

10. The circuit system of claim 1 , wherein the first integrated circuit die further comprises accessor circuits that access the second memory circuits through the die-to-die connections between the first and second integrated circuit dies, wherein each of the accessor circuits is allocated to a physical address space in the second memory circuits, and wherein the physical address space allocated to a first one of the accessor circuits overlaps with the physical address space allocated to a second one of the accessor circuits.

11. The circuit system of claim 10 , wherein the second integrated circuit die further comprises memory mapping circuits that map a logical address space received from the first integrated circuit die to the physical address space in the second memory circuits, and wherein the memory mapping circuits provide access control to the second memory circuits from the core logic region.

12. The circuit system of claim 1 , wherein a software compiler determines an optimal usage and configuration of resources in the first and second integrated circuit dies for a workload, and wherein the software compiler physically aligns logic resources in the core logic region with the second memory circuits to maximize memory access bandwidth during runtime.

13. The circuit system of claim 1 , wherein the second integrated circuit die further comprises compute logic circuits.

14. A three dimensional circuit system comprising:
a first integrated circuit die comprising a core logic region and a peripheral region, wherein the core logic region comprises first memory circuits and logic circuits, and wherein the peripheral region comprises second memory circuits; and
a second integrated circuit die comprising third memory circuits, wherein the first and second integrated circuit dies are coupled together in a vertically stacked configuration, wherein the logic circuits are coupled to access the first, second, and third memory circuits, wherein the second memory circuits have a different memory capacity and a different memory access bandwidth than the third memory circuits, and wherein the third memory circuits have a different memory capacity and a different memory access bandwidth than the first memory circuits,
wherein each of the third memory circuits comprises first level memories and a second level memory, wherein the core logic region further comprises memory direct access circuits, and wherein each of the memory direct access circuits has access to one of the first level memories and a partition of the second level memory in one of the third memory circuits.

15. The three dimensional circuit system of claim 14 , wherein the first integrated circuit die further comprises accessor circuits that access the third memory circuits, wherein each of the accessor circuits is allocated to a physical address space in the third memory circuits, a

Assignees

• Intel Corp

Inventors

• Weber Scott
• Khan Jawad
• Ganusov Ilya
• Langhammer Martin
• Adiletta Matthew
• Magee Terence
• Fazio Albert
• Coulson Richard
• Gutala Ravi
• Dasu Aravind
• Iyer Mahesh

Classifications

• H10W90/00

  Package configurations · CPC title

• G06F3/0655 Primary

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0673

  Single storage device · CPC title

• G11C11/56 Primary

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title