Three dimensional circuit systems and methods having memory hierarchies
US-11789641-B2 · Oct 17, 2023 · US
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Fazio Albert patents
Fazio Albert is listed as an inventor on 9 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Fazio Albert |
| Total patents | 9 |
| First publication | Mar 29, 2018 |
| Latest publication | Oct 17, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Stacked two-level backend memory
US-2022415892-A1 · Dec 29, 2022 · US
Three Dimensional Circuit Systems And Methods Having Memory Hierarchies
US-2022405005-A1 · Dec 22, 2022 · US
Scalable bandwidth non-volatile memory
US-11010061-B2 · May 18, 2021 · US
Memory preset adjustment based on adaptive calibration
US-10679698-B2 · Jun 9, 2020 · US
Scalable bandwidth non-volatile memory
US-2019332278-A1 · Oct 31, 2019 · US
Scalable bandwidth non-volatile memory
US-10331360-B2 · Jun 25, 2019 · US
Memory preset adjustment based on adaptive calibration
US-2019043571-A1 · Feb 7, 2019 · US
Scalable bandwidth non-volatile memory
US-2018088834-A1 · Mar 29, 2018 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 9 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C13/0004 | 6 |
| G06F13/1657 | 4 |
| G06F12/0238 | 4 |
| G06F3/0644 | 4 |
| G06F3/0613 | 4 |