Three dimensional circuit systems and methods having memory hierarchies
US-11789641-B2 · Oct 17, 2023 · US
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Magee Terence patents
Magee Terence is listed as an inventor on 7 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Magee Terence |
| Total patents | 7 |
| First publication | May 3, 2016 |
| Latest publication | Oct 17, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Input Output Banks of a Programmable Logic Device
US-2023140547-A1 · May 4, 2023 · US
Source Synchronous Partition of an SDRAM Controller Subsystem
US-2023123826-A1 · Apr 20, 2023 · US
Techniques For Synchronous Accesses To Storage Circuits
US-2023118912-A1 · Apr 20, 2023 · US
Three Dimensional Circuit Systems And Methods Having Memory Hierarchies
US-2022405005-A1 · Dec 22, 2022 · US
High-speed serial data interface for a physical layer interface
US-9557766-B1 · Jan 31, 2017 · US
Receivers and methods of enabling the calibration of circuits receiving input data
US-9331701-B1 · May 3, 2016 · US
Recent patents
Latest publications not already listed above.
No data yet.
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 5 |
| Xilinx Inc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F3/0673 | 3 |
| H10W90/00 | 2 |
| G06F3/0655 | 2 |
| G06F3/061 | 2 |
| G11C11/56 | 2 |