Active interposer for localized programmable integrated circuit reconfiguration

Patent metadata

Field	Value
Publication number	US-10291397-B2
Application number	US-201615381981-A
Country	US
Kind code	B2
Filing date	Dec 16, 2016
Priority date	Dec 16, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.

First claim

What is claimed is:

1. An integrated circuit package, comprising:
a package substrate;
an interposer mounted on the package substrate; and
an integrated circuit die mounted on the interposer, wherein the interposer includes memory that stores configuration data for the integrated circuit die.

2. The integrated circuit package of claim 1 , wherein the interposer has an active side at which the memory is formed, wherein the integrated circuit die has an active side at which logic circuits are formed, and wherein the active side of the interposer faces the active side of the integrated circuit die.

3. The integrated circuit package of claim 2 , further comprising:
microbumps that are interposed between the active side of the interposer and the active side of the integrated circuit die and that couple the memory to the logic circuits.

4. The integrated circuit package of claim 2 , wherein the logic circuits on the integrated circuit die are organized into logic sectors, and wherein the memory selectively configures at least one of the logic sectors with the configuration data.

5. The integrated circuit package of claim 1 , wherein the integrated circuit die includes decryption and decompression circuitry for decrypting and decompressing the configuration data.

6. The integrated circuit package of claim 1 , wherein the interposer includes decryption and decompression circuitry for decrypting and decompressing the configuration data.

7. The integrated circuit package of claim 1 , further comprising:
an additional integrated circuit die that includes additional memory for storing additional configuration data.

8. The integrated circuit package of claim 7 , further comprising:
a heat sink that is directly attached to the integrated circuit die and the additional integrated circuit die.

9. The integrated circuit package of claim 8 , wherein the interposer has a backside that faces the package substrate, wherein the additional integrated circuit die has an active side at which the additional memory is formed, and wherein the active side of the additional integrated circuit die faces the package substrate.

10. The integrated circuit package of claim 8 , wherein the additional integrated circuit die has an active side at which the additional memory is formed, and wherein the active side of the additional integrated circuit die faces the active side of the interposer.

11. The integrated circuit package of claim 7 , wherein the additional integrated circuit die has an active side at which the additional memory is formed, wherein the active side of the additional integrated circuit die faces the active side of the interposer, and wherein the additional integrated circuit die is mounted directly on the package substrate.

Assignees

• Intel Corp

Inventors

• Mcelheny Peter John
• Dasu Aravind

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/721

  of bump connectors · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title