Package comprising integrated devices coupled through a metallization layer

Patent metadata

Field	Value
Publication number	US-11784157-B2
Application number	US-202117339830-A
Country	US
Kind code	B2
Filing date	Jun 4, 2021
Priority date	Jun 4, 2021
Publication date	Oct 10, 2023
Grant date	Oct 10, 2023

Abstract

A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

First claim

What is claimed is:

1. A package comprising:
a first integrated device including a plurality of first pillar interconnects;
an encapsulation layer at least partially encapsulating the first integrated device, wherein the encapsulation layer is located between two or more first pillar interconnects from the plurality of first pillar interconnects;
a metallization portion coupled to (i) the plurality of first pillar interconnects of the first integrated device and (ii) the encapsulation layer,
wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects,
wherein the plurality of first pillar interconnects is coupled to a bottom side of the plurality of metallization layer interconnects; and

a second integrated device including a plurality of second pillar interconnects, wherein the second integrated device is coupled to a top side of the plurality of metallization layer interconnects through the plurality of second pillar interconnects and a plurality of solder interconnects;
a plurality of under bump metallization (UBM) interconnects coupled to at least part of the plurality of metallization layer interconnects;
a plurality of package pillar interconnects coupled to the plurality of UBM interconnects; and
a second plurality of solder interconnects coupled to and touching the plurality of package pillar interconnects, and
wherein the plurality of package pillar interconnects are free of being touched by any encapsulation layer,
wherein the plurality of package pillar interconnects are located laterally to the second integrated device,
wherein a frontside of the second integrated device faces the metallization portion, and
wherein a frontside of the first integrated device faces the metallization portion.

2. The package of claim 1 , wherein a second pillar interconnect from the plurality of the second pillar interconnects vertically overlaps with a first pillar interconnect from the plurality of first pillar interconnects.

3. The package of claim 1 , wherein at least two second pillar interconnects from a row second pillar interconnects from the plurality of second pillar interconnects vertically overlaps with at least two first pillar interconnects from a row of first pillar interconnects from the plurality of first pillar interconnects.

4. The package of claim 1 ,
wherein a first pillar interconnect from the plurality of the first pillar interconnects is coupled to a bottom side of a first metallization layer interconnect from the plurality of metallization layer interconnects, and
wherein a second pillar interconnect from the plurality of second pillar interconnects is coupled to a top side of the first metallization layer interconnect.

5. The package of claim 1 , wherein the second integrated device at least partially overlaps vertically with the first integrated device.

6. The package of claim 1 , wherein the plurality of first pillar interconnects is directly coupled to at least part of the plurality of metallization layer interconnects.

7. The package of claim 1 , wherein the first integrated device is configured to be coupled to the second integrated device through the plurality of metallization layer interconnects.

8. The package of claim 1 , wherein the first integrated device is configured to be electrically coupled to the second integrated device through an electrical path that includes a pillar interconnect from the plurality of first pillar interconnects, the metallization portion, a solder interconnect from the plurality of solder interconnect and a pillar interconnect from the plurality of second pillar interconnects.

9. The package of claim 1 , wherein the plurality of metallization layer interconnects includes a plurality of redistribution layer (RDL) interconnects.

10. The package of claim 1 , further comprising an underfill located between the second integrated device and the plurality of metallization layer interconnects.

11. The package of claim 1 ,
wherein the frontside of the first integrated device faces the plurality of metallization layer interconnects,
wherein the frontside of the second integrated device faces the plurality of metallization layer interconnects,
wherein the encapsulation layer is located between the first integrated device and the metallization portion, and
wherein the encapsulation layer touches (i) the frontside of the first integrated device and (ii) a side surface of the first integrated device.

12. The package of claim 1 , wherein at least one metallization layer interconnect includes a side profile that includes a U-shape and/or a V-shape.

13. The package of claim 1 , further comprising a backside lamination layer located over a backside of the first integrated device.

14. The package of claim 1 , wherein the plurality of metallization layer interconnects includes one metal layer.

15. The package of claim 1 ,
wherein the first integrated device includes a first bare semiconductor die, and
wherein the second integrated device includes a second bare semiconductor die.

16. An apparatus comprising:
a first integrated device comprising a plurality of first pillar interconnects;
means for encapsulation at least partially encapsulating the first integrated device, wherein the means for encapsulation is located between two or more first pillar interconnects from the plurality of first pillar interconnects;
a metallization portion coupled to (i) the first plurality of pillar interconnects of the first integrated device and (ii) the means for encapsulation,
wherein the metallization portion includes at least one passivation layer and means for metallization interconnection, and
wherein the plurality of first pillar interconnects is coupled to a bottom side of the means for metallization interconnection;

a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to a top side of the metallization interconnection through the plurality of second pillar interconnects and a first plurality of solder interconnects;
a plurality of package pillar interconnects coupled to the top side of the metallization interconnection, wherein the plurality of package pillar interconnects are located laterally to the second integrated device, and
a second plurality of solder interconnects coupled to and touching the plurality of package pillar interconnects,
wherein a frontside of the second integrated device faces the metallization portion, and
wherein a frontside of the first integrated device faces the metallization portion.

17. The apparatus of claim 16 , wherein a second pillar interconnect from the plurality of the second pillar interconnects vertically overlaps with a first pillar interconnect from the plurality of the first pillar interconnects.

18. The apparatus of claim 16 , wherein at least two second pillar interconnects from a row second pillar interconnects from the plurality of second pillar interconnects vertically overlaps with at least two first pillar interconnects from a row of first pillar interconnects from the plurality of first pillar interconnects.

19. The apparatus of claim 16 ,
wherein a first pillar interconnect from the plurality of first pillar interconnects is coupled to the bottom side of the means for metallization interconnection, and
wherein a second pillar interconnect from the plurality of second pillar interconnects is coupled to the top side of the means for metallization interconnection.

Assignees

• Qualcomm Inc

Inventors

• Weng Li-Sheng
• Paynter Charles David
• Lane Ryan
• Xu Jianwen
• Stone William

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07254

  changes in dispositions · CPC title