Semiconductor structure and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-11244906-B2
Application number	US-202016881002-A
Country	US
Kind code	B2
Filing date	May 22, 2020
Priority date	May 22, 2020
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion.

First claim

What is claimed is:

1. A package structure, comprising:
a first semiconductor die comprising a semiconductor substrate, an interconnect structure, and a first redistribution circuit structure, the semiconductor substrate comprising a first portion and a second portion disposed on the first portion, the interconnect structure being disposed on the second portion, the first redistribution circuit structure being disposed on and electrically connected to the interconnect structure, and a first lateral dimension of the first portion being greater than a second lateral dimension of the second portion;
a second semiconductor die disposed on the first semiconductor die;
first conductive pillars disposed on and electrically connected to the first redistribution circuit structure of the first semiconductor die; and
a first insulating encapsulation disposed on the first portion, the first insulating encapsulation laterally encapsulating the second semiconductor die, the first conductive pillars and the second portion.

2. The structure as claimed in claim 1 , wherein the first insulating encapsulation covers sidewalls of the second portion, and sidewalls of the first insulating encapsulation are substantially aligned with sidewalls of the first portion.

3. The structure as claimed in claim 1 , wherein the first insulating encapsulation comprises a body portion and a ring portion, the body portion laterally encapsulating the second semiconductor die and the first conductive pillars, the ring portion extending along sidewalls of the interconnect structure, sidewalls of the first redistribution circuit structure and the sidewalls of the second portion.

4. The structure as claimed in claim 1 further comprising:
second conductive pillars;
a second insulating encapsulation laterally encapsulating the second conductive pillars, the first insulating encapsulation and the first portion; and
a second redistribution circuit structure disposed on the second semiconductor die, the first conductive pillars, the second conductive pillars, the first insulating encapsulation and the second insulating encapsulation.

5. The structure as claimed in claim 4 , wherein the first redistribution circuit structure is a fan-in redistribution circuit structure, and the second redistribution circuit structure is a fan-out redistribution circuit structure.

6. The structure as claimed in claim 4 , wherein the interconnect structure and the first redistribution circuit structure are spaced apart from the second insulating encapsulation by the first insulating encapsulation.

7. The structure as claimed in claim 4 further comprising:
a third redistribution circuit structure disposed over the first portion, the second conductive pillars and the second insulating encapsulation, the second and third redistribution circuit structures being disposed at opposite sides of the second conductive pillars.

8. A package structure, comprising:
a first semiconductor die comprising a first semiconductor substrate, a first interconnect structure and a first bonding structure, the first semiconductor substrate comprising a first portion and a second portion disposed on the first portion, the first interconnect structure being disposed on the second portion, the first bonding structure being disposed on and electrically connected to the first interconnect structure, and a first lateral dimension of the first portion being greater than a second lateral dimension of the second portion;
a second semiconductor die comprising a second semiconductor substrate, a second interconnect structure disposed on the second semiconductor substrate and a second bonding structure disposed on the second interconnect structure, the second semiconductor die being electrically connected to the first semiconductor die through the first and second bonding structures; and
a first insulating encapsulation disposed on the first portion of the first semiconductor substrate, the first insulating encapsulation laterally encapsulating the second semiconductor die and the second portion of the first semiconductor substrate.

9. The structure as claimed in claim 8 , wherein the first insulating encapsulation covers sidewalls of the second portion of the first semiconductor substrate, and sidewalls of the first insulating encapsulation are substantially aligned with sidewalls of the first portion of the first semiconductor substrate.

10. The structure as claimed in claim 8 , wherein the first insulating encapsulation comprises a body portion and a ring portion, the body portion laterally encapsulating the second semiconductor die, the ring portion extending along sidewalls of the interconnect structure, sidewalls of the first bonding structure and the sidewalls of the second portion of the first semiconductor substrate.

11. The structure as claimed in claim 8 further comprising:
conductive pillars;
a second insulating encapsulation laterally encapsulating the conductive pillars, the first insulating encapsulation and the first portion of the first semiconductor substrate; and
a first fan-out redistribution circuit structure disposed on the second insulating encapsulation and electrically connected to the first semiconductor die and the conductive pillars.

12. The structure as claimed in claim 11 , wherein the first semiconductor die comprises through semiconductor vias electrically connected to the first redistribution circuit structure.

13. The structure as claimed in claim 11 , wherein the first interconnect structure, the second interconnect structure, the first bonding structure and the second bonding structure are spaced apart from the second insulating encapsulation by the first insulating encapsulation.

14. The structure as claimed in claim 8 further comprising:
a second fan-out redistribution circuit structure disposed on the second semiconductor die, the conductive pillars, the first insulating encapsulation and the second insulating encapsulation.

15. The structure as claimed in claim 14 further comprising:
a die attachment film disposed between the second semiconductor die and the second fan-out redistribution circuit structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Tzu-Sung
• Hsieh Cheng-Chieh
• Lin Hsiu-Jen
• Tsai Hui-Jung
• Kuo Hung-Yi
• Tsai Hao-Yi
• Tseng Ming-Hung
• Lin Yen-Liang
• Lu Chun-Ti
• Weng Chung-Ming

Classifications

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title