Package comprising an integrated device and an offset memory device
US-2025379135-A1 · Dec 11, 2025 · US
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Lane Ryan patents
Lane Ryan is listed as an inventor on 23 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Lane Ryan |
| Total patents | 23 |
| First publication | May 9, 2019 |
| Latest publication | Dec 11, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Package comprising an interposer package with metallization portions, and a passive device and a bridge between the metallization portions
US-2025343176-A1 · Nov 6, 2025 · US
Package comprising substrates, integrated devices and a heat sink
US-2025293112-A1 · Sep 18, 2025 · US
Stacked integrated circuit devices including logic die and memory stacks
US-2025246582-A1 · Jul 31, 2025 · US
Package comprising integrated devices and a passive device
US-2025201786-A1 · Jun 19, 2025 · US
Package comprising a bridge located between metallization portions
US-2025096207-A1 · Mar 20, 2025 · US
Package comprising a substrate with an embedded frame
US-2025069965-A1 · Feb 27, 2025 · US
Stacked integrated circuit devices
US-2025062285-A1 · Feb 20, 2025 · US
Semiconductor device with multiple stacked passive devices
US-2024421128-A1 · Dec 19, 2024 · US
Providing a lower inductance path in a routing substrate for a capacitor, and related electronic devices and fabrication methods
US-12160952-B2 · Dec 3, 2024 · US
Recent patents
Latest publications not already listed above.
Substrate employing core with cavity embedding reduced height electrical device(s), and related integrated circuit (ic) packages and fabrication methods
US-2024371736-A1 · Nov 7, 2024 · US
Providing a lower inductance path in a routing substrate for a capacitor, and related electronic devices and fabrication methods
US-2024107665-A1 · Mar 28, 2024 · US
Package comprising a chiplet located between an integrated device and a metallization portion
US-2024072032-A1 · Feb 29, 2024 · US
Package comprising a chiplet located between two metallization portions
US-2024071993-A1 · Feb 29, 2024 · US
Package with a substrate comprising embedded stacked trench capacitor devices
US-2024038831-A1 · Feb 1, 2024 · US
Package comprising integrated devices coupled through a metallization layer
US-11784157-B2 · Oct 10, 2023 · US
Package comprising a substrate and a high-density interconnect integrated device coupled to the substrate
US-11605594-B2 · Mar 14, 2023 · US
Package comprising integrated devices coupled through a metallization layer
US-2022392867-A1 · Dec 8, 2022 · US
Patch substrate configured as a shield located over a cavity of a board
US-11452246-B2 · Sep 20, 2022 · US
Package cavity for enhanced device performance with an integrated passive device
US-2021375845-A1 · Dec 2, 2021 · US
Patch substrate configured as a shield located over a cavity of a board
US-2021307218-A1 · Sep 30, 2021 · US
Package comprising a substrate and a high-density interconnect integrated device coupled to the substrate
US-2021296246-A1 · Sep 23, 2021 · US
Embedded thermal enhancement structures for molded integrated circuit packages
US-2019139852-A1 · May 9, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 23 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/00 | 18 |
| H10W90/724 | 17 |
| H10W90/701 | 17 |
| H10W90/401 | 14 |
| H10W70/611 | 14 |