Stacked semiconductor package assemblies including double sided redistribution layers

Patent metadata

Field	Value
Publication number	US-2019103386-A1
Application number	US-201715721257-A
Country	US
Kind code	A1
Filing date	Sep 29, 2017
Priority date	Sep 29, 2017
Publication date	Apr 4, 2019
Grant date	—

Abstract

A semiconductor device package comprises a bottom electronic device, an interposer module, a top electronic device, and a double sided redistribution layer (RDL) structure. The interposer module includes a plurality of conductive vias. The top electronic device has an active surface and is disposed above the bottom electronic device and above the interposer module. The double sided RDL structure is disposed between the bottom electronic device and the top electronic device. The active surface of the bottom electronic device faces toward the double sided RDL structure. The active surface of the top electronic device faces toward the double sided RDL structure. The double sided RDL structure electrically connects the active surface of the bottom electronic device to the active surface of the top electronic device. The double sided RDL structure electrically connects the active surface of the top electronic device to the interposer module.

First claim

1 . A semiconductor device package comprising:
a bottom electronic device having an active surface; an interposer module including a plurality of conductive vias; a top electronic device having an active surface and disposed above the bottom electronic device and above the interposer module; and a double sided redistribution layer (RDL) structure disposed between the bottom electronic device and the top electronic device, the active surface of the bottom electronic device facing toward the double sided RDL structure, the active surface of the top electronic device facing toward the double sided RDL structure, the double sided RDL structure electrically connecting the active surface of the bottom electronic device to the active surface of the top electronic device, the double sided RDL structure electrically connecting the active surface of the top electronic device to the interposer module.

2 . The semiconductor device package of claim 1 , further comprising:
a second RDL structure disposed below the bottom electronic device and below the interposer module, the interposer module electrically connecting the double sided RDL structure to the second RDL structure.

3 . The semiconductor device package of claim 2 , further comprising a conductive post electrically connecting the double sided RDL structure to the second RDL.

4 . The semiconductor device package of claim 1 , wherein the double sided RDL structure electrically connects the active surface of the bottom electronic device to the interposer module.

5 . The semiconductor device package of claim 1 , wherein the interposer module is a through-silicon via (TSV) module.

6 . The semiconductor device package of claim 1 , further comprising:
a package body encapsulating the bottom electronic device and the interposer module, wherein the package body covers a back surface of the bottom electronic device opposite to the active surface of the bottom electronic device.

7 . The semiconductor device package of claim 6 , further comprising:
a thermal conducting component extending between the back surface of the bottom electronic device and an external surface of the package body.

8 . The semiconductor device package of claim 1 , further comprising:
a plurality of contact pads disposed adjacent to the active surface of the bottom electronic device; and a plurality of connectors disposed between the contact pads and the double sided RDL structure, the connectors electrically connecting the contact pads to the double sided RDL structure, the connectors including solder.

9 . The semiconductor device package of claim 1 , wherein the interposer component includes a routing layer electrically connecting a first one of the conductive vias to a second one of the conductive vias.

10 . The semiconductor device package of claim 1 , wherein the semiconductor device package comprises a plurality of bottom electronic devices including the bottom electronic device, or comprises a plurality of top electronic devices including the top electronic device.

11 .- 22 . (canceled)

23 . The semiconductor device package of claim 1 , further comprising:
a plurality of contact pads disposed adjacent to the active surface of the top electronic device; and a plurality of connectors disposed between the contact pads and the double sided RDL structure, the connectors electrically connecting the contact pads to the double sided RDL structure, the connectors including solder.

24 . The semiconductor device package of claim 23 , further comprising:
an underfill covering the active surface of the top electronic device and the connectors.

25 . The semiconductor device package of claim 1 , wherein the double sided RDL structure comprises a top RDL and a bottom RDL, and at least some traces of the top RDL are electrically connected to at least some traces of the bottom RDL.

26 . The semiconductor device package of claim 2 , wherein the second RDL structure comprises a top RDL and a bottom RDL, and at least some traces of the top RDL are electrically connected to at least some traces of the bottom RDL.

27 . The semiconductor device package of claim 2 , further comprising:
one or more connecting elements electrically connected to the second RDL structure.

28 . A semiconductor device package comprising:
a top electronic device having an active surface; a bottom electronic device having an active surface facing toward the active surface of the top electronic device, and a back surface opposite to the active surface of the bottom electronic device; an interposer module; a package body encapsulating the interposer module and the bottom electronic device and covering the back surface of the bottom electronic device; and a double sided redistribution layer (RDL) structure disposed between the bottom electronic device and the top electronic device, the double sided RDL structure electrically connecting the active surface of the bottom electronic device to the active surface of the top electronic device, and electrically connected to the interposer module.

29 . The semiconductor device package of claim 28 ,
wherein the interposer module extends through the package body and includes a plurality of conductive vias electrically connected to the double sided RDL structure.

30 . The semiconductor device package of claim 28 , further comprising:
a conductive post extending through the package body and electrically connected to the double sided RDL structure.

31 . The semiconductor device package of claim 28 , further comprising:
a thermal conducting component extending between the back surface of the bottom electronic device and an external surface of the package body.

32 . The semiconductor device package of claim 28 , further comprising:
a plurality of connectors disposed between the active surface of the bottom electronic device and the double sided RDL structure, the connectors including solder.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chen William T
• Hunt John Richard
• Hung Chih-Pin
• Wang Chen-Chao
• Huang Chih-Yi

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title