Image sensor chip

Patent metadata

Field	Value
Publication number	US-11776982-B2
Application number	US-202017134699-A
Country	US
Kind code	B2
Filing date	Dec 28, 2020
Priority date	May 7, 2020
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

An image sensor chip includes a lower chip, an upper chip stacked on the lower chip and including a photoelectric element, a via hole penetrating through the upper chip and penetrating through at least a portion of the lower chip, and a conductive connection layer electrically connecting the lower chip and the upper chip to each other in the via hole. The upper chip includes an upper substrate, an upper isolation layer and an upper element on the upper substrate, a connection contact plug, and a multilayer interconnection line electrically connected to the connection contact plug. A distance between an upper surface of the connection contact plug and an upper surface of the upper isolation layer is greater than a distance between an upper surface of an upper gate electrode of the upper element and an upper surface of the upper isolation layer.

First claim

What is claimed is:

1. An image sensor chip comprising:
a lower chip;
an upper chip stacked on the lower chip and including a first photoelectric element;
a first via hole penetrating through the upper chip and penetrating through at least a portion of the lower chip; and
a first conductive connection layer in the first via hole,
wherein the lower chip includes a lower substrate having a first surface and a second surface opposing each other, a lower interconnection structure including a first lower pad on the first surface of the lower substrate, and a lower insulating structure covering the lower interconnection structure on the first surface of the lower substrate,
the upper chip further includes an upper substrate having a third surface and a fourth surface opposing each other, an upper element and an upper interconnection structure below the third surface of the upper substrate, and an upper insulating structure covering the upper element and the upper interconnection structure below the third surface of the upper substrate,
a lower surface of the upper insulating structure contacts an upper surface of the lower insulating structure,
the third surface of the upper substrate and the first surface of the lower substrate face each other,
the upper interconnection structure includes an upper circuit interconnection structure and an upper interconnection line structure,
the upper circuit interconnection structure includes a circuit contact plug electrically connected to the upper element, and a multilayer circuit interconnection line electrically connected to the circuit contact plug,
the upper interconnection line structure includes a connection contact plug and a multilayer interconnection line below and contacting the connection contact plug,
the first conductive connection layer is in contact with the connection contact plug in the upper chip and the first lower pad in the lower chip and is spaced apart from the multilayer interconnection line in the upper chip,
the first conductive connection layer is configured to electrically connect the connection contact plug and the first lower pad to each other,
the upper element includes a transistor including a source/drain region, a gate dielectric layer and a gate electrode,
at least a portion of the gate electrode is at the same level as a portion of the connection contact plug,
the gate electrode has an upper surface contacting the gate dielectric layer and a lower surface opposing the upper surface of the gate electrode, and
a lower surface of the connection contact plug is at a lower level than the lower surface of the gate electrode.

2. The image sensor chip of claim 1 ,
wherein the circuit contact plug includes a first contact plug, in contact with the source/drain region, and a second contact plug in contact with the gate electrode,
the connection contact plug includes the same material as at least one of the first contact plug and the second contact plug,
the gate dielectric layer includes a lower surface contacting the gate electrode and an upper surface contacting an active region of the upper substrate,
the lower surface of the connection contact plug is substantially at a same level as a lower surface of at least one of the first contact plug and the second contact plug,
the connection contact plug includes a first conductive material, and
the multilayer interconnection line includes a second conductive material different from the first conductive material.

3. The image sensor chip of claim 2 , wherein each of the connection contact plug, the first contact plug, and the second contact plug includes a plug layer and a barrier layer, and
the barrier layer covers a side surface and a bottom surface of the plug layer.

4. The image sensor chip of claim 3 , wherein the multilayer interconnection line comprises:
a lower interconnection line layer;
an upper interconnection line layer; and
a middle interconnection line layer disposed between the lower interconnection line layer and the upper interconnection line layer to electrically connect the lower interconnection line layer and the upper interconnection line layer to each other, and
wherein the lower interconnection line layer is in contact with a surface of the plug layer of the connection contact plug.

5. The image sensor chip of claim 1 , wherein the upper chip further includes an upper isolation layer defining an upper active region,
the first via hole penetrates through a portion of the upper isolation layer, and
the connection contact plug overlaps the upper isolation layer adjacent to the first via hole.

6. The image sensor chip of claim 1 , wherein the connection contact plug comprises:
first bar patterns extending in a first horizontal direction, and disposed parallel to each other;
second bar patterns extending in the first horizontal direction while facing the first bar patterns, and disposed parallel to each other;
third bar patterns extending in a second horizontal direction, perpendicular to the first horizontal direction, and disposed parallel to each other; and
fourth bar patterns extending in the second horizontal direction while facing the third bar patterns, and disposed parallel to each other.

7. The image sensor chip of claim 5 , wherein an upper end of a sidewall of the first via hole overlaps the connection contact plug in a vertical direction.

8. The image sensor chip of claim 7 , wherein a lower end of the sidewall of the first via hole does not overlap the connection contact plug in the vertical direction.

9. The image sensor chip of claim 5 , wherein a maximum thickness of the upper isolation layer is greater than a distance between the connection contact plug and the upper substrate.

10. The image sensor chip of claim 1 , wherein a portion of the connection contact plug, in contact with the first conductive connection layer, comprises:
a first side portion;
a second side portion; and
an inflection portion disposed between the first side portion and the second side portion and extending in a direction substantially parallel to the third surface.

11. The image sensor chip of claim 10 , wherein in the connection contact plug, a thickness of a first portion having the first side portion is greater than a thickness of a second portion having the second side portion, and
a distance between the second side portion and the upper substrate is greater than a distance between the first side portion and the upper substrate.

12. The image sensor chip of claim 1 , wherein the first photoelectric element is disposed in the upper substrate, and
wherein the upper chip comprises:
a second photoelectric element disposed in the upper substrate;
a backside insulating layer on the fourth surface of the upper substrate;
a microlens overlapping the first photoelectric element on the backside insulating layer; and
a light shielding layer overlapping the second photoelectric element on the backside insulating layer.

13. The image sensor chip of claim 12 , wherein the light shielding layer is formed of the same material as the first conductive connection layer.

14. The image sensor chip of claim 1 , further comprising:
a second via hole penetrating through the upper chip and penetrating through at least a portion of the lower chip;
a second conductive connection layer in the second via hole; and
a chip pad electrically connected to the second conductive connection layer on the fourth surface of the upper substrate.

15. An image sensor chip comprising:
a lower chip;
an upper chip stacked on the lower chip and including a photoelectric elem

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jang Minho
• Kwon Doowon
• Kim Dongchan
• Kim Bokwon
• BYUN Kyungrae
• Ahn Jungchak
• Yeo Hyunyoung

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10F39/8063

  Microlenses · CPC title

• H10F39/8057

  Optical shielding · CPC title

• H10F39/8053

  Colour filters · CPC title