Via structures including etch-delay structures and semiconductor devices having via plugs

Patent metadata

Field	Value
Publication number	US-9728572-B2
Application number	US-201414561854-A
Country	US
Kind code	B2
Filing date	Dec 5, 2014
Priority date	Feb 3, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.

First claim

What is claimed is:

1. A semiconductor device comprising an upper device disposed on a lower device,
wherein the lower device comprises:
a lower substrate;
a lower plug pad disposed on the lower substrate; and
a lower interlayer insulating layer on the lower plug pad,

wherein the upper device comprises:
an upper substrate;
an etch-delay structure under the upper substrate;
an upper plug pad disposed on a bottom surface of the upper substrate,
an upper interlayer dielectric layer on the upper plug pad; and
a conductive via plug extending through the upper substrate and configured to electrically contact the upper plug pad and the lower plug pad,

wherein the conductive via plug comprises:
a first conductive portion having a conductive surface that is configured to contact the upper plug pad and the etch-delay structure;
a second conductive portion having a conductive surface that is configured to contact the lower plug pad but to not contact the etch-delay structure; and
first and second opposing conductive sidewalls that both extend from a top end of the conductive via plug to a bottom end of the conductive via plug, the first conductive sidewall configured to contact the etch-delay structure and the second conductive sidewall configured to not contact the etch-delay structure.

2. The semiconductor device of claim 1 , wherein the first conductive portion of the conductive via plug partially penetrates the upper interlayer dielectric layer, and
the second conductive portion of the conductive via plug completely penetrates the upper interlayer dielectric layer and partially penetrates the lower interlayer insulating layer.

3. The semiconductor device of claim 1 , wherein the etch-delay structure includes a trench in the upper substrate and silicon oxide in the trench.

4. The semiconductor device of claim 3 , wherein the etch-delay structure is a first etch-delay structure and wherein the upper device further comprises a second etch-delay structure in the upper interlayer dielectric layer and including a conductor.

5. The semiconductor device of claim 1 , wherein the upper device further comprises a floating insulating layer surrounding the conductive via plug from a plan view.

6. The semiconductor device of claim 5 , wherein a portion of the floating insulating layer is in contact with the etch-delay structure.

7. The semiconductor device of claim 5 , wherein the floating insulating layer has a rim-shaped layout surrounding the conductive via plug from a plan view.

8. The semiconductor device of claim 5 , further comprising a capping insulating layer on the upper substrate,
wherein the capping insulating layer is materially in continuity with the floating insulating layer.

9. The semiconductor device of claim 8 , wherein the conductive via plug penetrates the capping insulating layer.

10. The semiconductor device of claim 1 , wherein the upper device further comprises an upper circuit and a dam pattern in the upper interlayer dielectric layer and including a same material,
wherein the dam pattern has a frame shape wholly surrounding the conductive via plug in four directions from a cross-sectional view.

11. The semiconductor device of claim 10 , wherein the upper circuit comprises multilayered upper interconnections extending horizontally and an upper via plug configured to vertically connect the upper interconnections,
wherein the dam pattern comprises panel patterns at a same level as the upper interconnections and a fence pattern at a same level as the upper via plug.

12. The semiconductor device of claim 10 , wherein the upper device further comprises a middle interlayer dielectric layer under the upper interlayer dielectric layer and the dam pattern and a buffer insulating layer under the middle interlayer dielectric layer,
wherein the middle interlayer dielectric layer includes an insulating material denser than the upper interlayer dielectric layer, and
the buffer insulating layer includes silicon oxide.

13. The semiconductor device of claim 10 , wherein a portion of the dam pattern is in contact with the conductive via plug.

14. The semiconductor device of claim 10 , wherein the upper device further comprises tap patterns on a top end portion of the dam pattern,
wherein the tap patterns include an insulating material denser than the upper interlayer dielectric layer.

15. A semiconductor device comprising:
a lower substrate;
a lower plug pad disposed on the lower substrate;
a lower interlayer dielectric layer surrounding the lower plug pad;
an upper plug pad disposed on the lower interlayer dielectric layer;
an upper interlayer dielectric layer surrounding the upper plug pad;
an upper substrate disposed on the upper interlayer dielectric layer;
an etch-delay structure disposed adjacent to an interface between the upper interlayer dielectric layer and the upper substrate; and
a conductive via plug configured to vertically penetrate the upper substrate, the conductive via plug having a first conductive portion having a conductive surface that is in contact with the upper plug pad and the etch-delay structure, a second conductive portion having a conductive surface that is in contact with the lower plug pad but not in contact with the etch-delay structure and having a larger vertical length than the first conductive portion, and first and second opposing conductive sidewalk that both extend from a top end of the conductive via plug to a bottom end of the conductive via plug, the first conductive sidewall configured to contact the etch-delay structure and the second conductive sidewall configured to not contact the etch-delay structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Byung-Jun
• Moon Chang-Rok
• Shin Seung-Hun
• Oh Seong-Ho
• Oh Tae-Seok
• Lee June-Taeg

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title