Packaging structure including interconnecs and packaging method thereof

Patent metadata

Field	Value
Publication number	US-10236273-B2
Application number	US-201715614056-A
Country	US
Kind code	B2
Filing date	Jun 5, 2017
Priority date	Jun 12, 2016
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

A packaging structure and a packaging method are provided. The packaging structure includes a carrier semiconductor structure including a carrier substrate, a carrier dielectric layer, and a carrier top conductive layer inside the carrier dielectric layer and having a top exposed by the carrier dielectric layer. The packaging structure also includes a top semiconductor structure including a top substrate, a first dielectric layer, a zeroth conductive layer, and a second dielectric layer, wherein a position of the zeroth conductive layer corresponds to a position of the carrier top conductive layer. Further, the packaging structure includes a conductive plug formed on one side of the zeroth conductive layer, and penetrating through the top substrate, the first dielectric layer, and the second dielectric layer, wherein the conductive plug is electrically connected to each of the zeroth conductive layer and the carrier top conductive layer.

First claim

What is claimed is:

1. A packaging structure, comprising:
a carrier semiconductor structure including a carrier substrate, a carrier dielectric layer on the carrier substrate, and a carrier interconnection structure inside the carrier dielectric layer, wherein the carrier interconnection structure includes a carrier top conductive layer having a top surface exposed by the carrier dielectric layer, wherein the top surface of the carrier top conductive layer is coplanar with a top surface of the carrier dielectric layer;
a top semiconductor structure inversely bonded to the carrier semiconductor structure, and including a first dielectric layer on a top substrate, a zeroth conductive layer on the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the zeroth conductive layer, wherein a position of the zeroth conductive layer corresponds to a position of the carrier top conductive layer; and
a conductive plug formed on one side of the zeroth conductive layer, and penetrating through the top substrate, the first dielectric layer, and the second dielectric layer, wherein the conductive plug is electrically connected to each of the zeroth conductive layer and the carrier top conductive layer.

2. The packaging structure according to claim 1 , wherein:
the zeroth conductive layer is made of a material including one or more of copper and aluminum.

3. The packaging structure according to claim 1 , wherein:
the conductive plug includes a first plug portion penetrating through the top substrate and the first dielectric layer, and a second plug portion penetrating through the second dielectric layer;
a size of the second plug portion is smaller than a size of the first plug portion along a direction parallel to the top substrate;
a sidewall of the second plug portion facing toward the zeroth conductive layer is in contact with the zeroth conductive layer; and
the sidewall of the second plug portion facing away from the zeroth conductive layer is connected to a sidewall of the first plug portion.

4. The packaging structure according to claim 3 , wherein:
a ratio of a top dimension of the second plug portion to a bottom dimension of the first plug portion is in a range of approximately ⅓-⅔.

5. The packaging structure according to claim 1 , wherein:
the conductive plug includes a third plug portion penetrating through the top substrate and the first dielectric layer, and a fourth plug portion penetrating through the second dielectric layer;
a sidewall of the fourth plug portion is connected to a sidewall of the third plug portion; and
the sidewall of the fourth plug portion facing toward the zeroth conductive layer is in contact with the zeroth conductive layer.

6. A packaging structure, comprising:
a carrier semiconductor structure including a carrier substrate, a carrier dielectric layer on the carrier substrate, and a carrier interconnection structure inside the carrier dielectric layer, wherein the carrier interconnection structure includes a carrier top conductive layer having a top exposed by the carrier dielectric layer;
a top semiconductor structure inversely bonded to the carrier semiconductor structure, and including a first dielectric layer on a top substrate, a zeroth conductive layer on the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the zeroth conductive layer, wherein a position of the zeroth conductive layer corresponds to a position of the carrier top conductive layer;
an adhesive layer formed between the second dielectric layer and the carrier dielectric layer; and
a conductive plug formed on one side of the zeroth conductive layer, and penetrating through the top substrate, the first dielectric layer, the adhesive layer, and the second dielectric layer, wherein the conductive plug is electrically connected to each of the zeroth conductive layer and the carrier top conductive layer.

7. The packaging structure according to claim 1 , further including:
an etch protection layer formed between the conductive plug, and each of the top substrate and the first dielectric layer.

8. The packaging structure according to claim 7 , wherein:
the etch protection layer is made of a material including one or more of silicon oxide, silicon nitride, and silicon oxynitride.

9. The packaging structure according to claim 7 , wherein:
a thickness of the etch protection layer is in a range of approximately 100 Å-5000 Å.

10. A packaging method, comprising:
providing a carrier semiconductor structure including a carrier substrate, a carrier dielectric layer on the carrier substrate, and a carrier interconnection structure inside the carrier dielectric layer, wherein the carrier interconnection structure includes a carrier top conductive layer having a top surface exposed by the carrier dielectric layer, wherein the top surface of the carrier top conductive layer is coplanar with a top surface of the carrier dielectric layer;
providing a top semiconductor structure including a first dielectric layer on a top substrate, a zeroth conductive layer on the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the zeroth conductive layer;
flipping the top semiconductor structure on the carrier semiconductor structure;
performing a bonding process on the top semiconductor structure and the carrier semiconductor structure, wherein a position of the zeroth conductive layer corresponds to a position of the carrier top conductive layer;
forming a conductive through hole on one side of the zeroth conductive layer by sequentially etching the top substrate, the first dielectric layer and the second dielectric layer along a direction from a back surface to a front surface of the top substrate, wherein the conductive through hole exposes the zeroth conductive layer and the carrier top conductive layer; and
forming a conductive plug to fill up the conductive through hole.

11. The method according to claim 10 , wherein:
the zeroth conductive layer is made of a material including one or more of copper and aluminum.

12. The method according to claim 10 , wherein forming the conductive through hole includes:
forming a first trench by sequentially etching the top substrate and the first dielectric layer along the direction from the back surface to the front surface of the top substrate, wherein the first trench exposes portions of the zeroth conductive layer and portions of the second dielectric layer contacting with the zeroth conductive layer;
forming an etch protection layer on a sidewall of the first trench; and
forming a second trench exposing the carrier top conductive layer by etching the second dielectric layer along the first trench, wherein the second trench and the first trench pass through each other to form the conductive through hole.

13. The method according to claim 12 , wherein:
a ratio of a size of the zeroth conductive layer exposed by the first trench to a bottom size of the first trench is in a range of approximately ⅓-⅔.

14. The method according to claim 12 , wherein:
the etch protection layer is made of a material including one or more of silicon oxide, silicon nitride, and silicon oxynitride.

15. The method according to claim 12 , wherein:
a thickness of the etch protection layer is in a range of approximately 100 Å-5000 Å.

16. The method according to claim 10 , wherein forming the conductive through hole includes:
forming a third trench by sequentially etching the top substrate and the first dielectric layer along the direction from the bac

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Wang Chong
• Zhang Hai Fang
• Liu Xuan Jie

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title