Multi-stacked device having TSV structure

Patent metadata

Field	Value
Publication number	US-9935037-B2
Application number	US-201715408977-A
Country	US
Kind code	B2
Filing date	Jan 18, 2017
Priority date	Jan 19, 2016
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on the first insulating layer, an intermediate device having an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer, an upper device having an upper substrate, a third insulating layer on the upper substrate, a second TSV bump on the third insulating layer, and a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad. An insulating first TSV spacer between the intermediate substrate and the TSV structure and an insulating second TSV spacer between the upper substrate and the TSV structure are spaced apart along a stacking direction.

First claim

What is claimed is:

1. A multi-stacked device, comprising:
a lower device including a lower substrate, a first insulating layer on the lower substrate, and a through-silicon via (TSV) pad on the first insulating layer;
an intermediate device including an intermediate substrate, a second insulating layer on the intermediate substrate, and a first TSV bump on the second insulating layer;
an upper device including an upper substrate, a third insulating layer on the upper substrate, and a second TSV bump on the third insulating layer; and
a TSV structure passing through the upper substrate, the third insulating layer, the second insulating layer, and the intermediate substrate to be connected to the first TSV bump, the second TSV bump, and the TSV pad,
wherein the intermediate device has an insulating first TSV spacer between the intermediate substrate and a lower portion of the TSV structure, the upper device has an insulating second TSV spacer between the upper substrate and an upper portion of the TSV structure, and a side surface of the TSV structure is in direct contact with the second insulating layer and the third insulating layer.

2. The multi-stacked device as claimed in claim 1 , wherein the first TSV bump is in direct contact with the second TSV bump, and a part of a bottom of the upper portion of the TSV structure is in contact with a part of the second TSV bump.

3. The multi-stacked device as claimed in claim 1 , wherein:
the lower portion of the TSV structure passes through the intermediate substrate and the upper portion of the TSV structure passes through the upper substrate;
a side surface of the lower portion of the TSV structure is in contact with the first TSV spacer; and
a side surface of the upper portion of the TSV structure is in contact with the second TSV spacer.

4. The multi-stacked device as claimed in claim 1 , wherein the lower device further includes:
a lower TSV interconnection on the first insulating layer; and
a lower TSV via plug perpendicularly connecting the lower TSV interconnection and the TSV pad.

5. The multi-stacked device as claimed in claim 1 , wherein the intermediate device further includes:
an intermediate TSV interconnection on the second insulating layer; and
an intermediate TSV via plug perpendicularly connecting the intermediate TSV interconnection and the first TSV bump.

6. The multi-stacked device as claimed in claim 1 , wherein the upper device further includes:
an upper TSV interconnection on the third insulating layer; and
an upper TSV via plug perpendicularly connecting the upper TSV interconnection and the second TSV bump.

7. The multi-stacked device as claimed in claim 1 , wherein:
the lower device further includes:
a lower cell metal layer on the first insulating layer in a cell area;
a lower cell via plug on the lower cell metal layer; and
a lower cell bump on the lower cell via plug; and
the intermediate device further includes:
an intermediate cell metal layer on the second insulating layer in the cell area;
an intermediate cell via plug on the intermediate cell metal layer; and
an intermediate cell bump on the intermediate cell via plug,
wherein the lower cell bump and the intermediate cell bump are connected electrically.

8. The multi-stacked device as claimed in claim 1 , wherein:
the intermediate device further includes:
an intermediate cell metal layer on the second insulating layer in a cell area;
an intermediate cell via plug on the intermediate cell metal layer; and
an intermediate cell bump on the intermediate cell via plug; and
the upper device further includes:
an upper cell metal layer on the third insulating layer in the cell area;
an upper cell via plug on the upper cell metal layer; and
an upper cell bump on the upper cell via plug,
wherein the intermediate cell bump and the upper cell bump are electrically connected.

9. The multi-stacked device as claimed in claim 1 , wherein:
the first TSV spacer electrically insulates the TSV structure from a bulk area of the intermediate substrate; and
the second TSV spacer electrically insulates the TSV structure from a bulk area of the upper substrate.

10. A multi-stacked device, comprising:
a lower device including a lower substrate, a plurality of first insulating layers on the lower substrate, and a through-silicon via (TSV) pad on the first insulating layers;
an intermediate device including an intermediate substrate, an insulating first TSV spacer passing through the intermediate substrate, a plurality of second insulating layers on the intermediate substrate, and a first TSV bump on the second insulating layers;
an upper device including an upper substrate, an insulating second TSV spacer passing through the upper substrate, a plurality of third insulating layers on the upper substrate, and a second TSV bump on the third insulating layers; and
a TSV structure passing through the upper substrate, the plurality of third insulating layers, the plurality of second insulating layers, and the intermediate substrate to be in contact with the second TSV bump and the TSV pad,
wherein:
the first TSV spacer electrically insulates the intermediate substrate from the TSV structure;
the second TSV spacer electrically insulates the upper substrate from the TSV structure; and
the first TSV spacer and the second TSV spacer are spaced apart from each other.

11. The multi-stacked device as claimed in claim 10 , wherein:
the first TSV spacer surrounds a lower portion of the TSV structure; and
the second TSV spacer surrounds an upper portion of the TSV structure.

12. The multi-stacked device as claimed in claim 10 , wherein:
the first insulating layers include a first lower interlayer insulating layer, a first intermediate interlayer insulating layer, and a first upper interlayer insulating layer;
the second insulating layers include a second lower interlayer insulating layer, a second intermediate interlayer insulating layer, and a second upper interlayer insulating layer;
the third insulating layers include a third lower interlayer insulating layer, a third intermediate interlayer insulating layer, and a third upper interlayer insulating layer;
a first end portion of the first TSV spacer is in contact with the second lower interlayer insulating layer, and
a second end portion of the second TSV spacer is in contact with the third lower interlayer insulating layer.

13. The multi-stacked device as claimed in claim 12 , wherein the TSV structure does not pass through the first insulating layers.

14. The multi-stacked device as claimed in claim 10 , wherein:
the lower device further includes:
memory cells and a lower cell metal layer in a cell area;
a lower peripheral metal layer and a lower TSV interconnection in a peripheral area; and
a lower TSV via plug perpendicularly connecting the lower TSV interconnection and the TSV pad;
the intermediate device further includes:
logic transistors and an intermediate cell metal layer in the cell area;
an intermediate peripheral metal layer and an intermediate TSV interconnection in the peripheral area; and
an intermediate TSV via plug perpendicularly connecting the intermediate TSV interconnection and the first TSV bump; and
the upper device further includes:
photodiodes and an upper cell metal layer in the cell area;
an upper peripheral metal layer and an upper TSV interconnection in the peripheral area; and
an upper TSV via plug perpendicularly connecting the upper TSV interconnection and the second TSV bump.

15. The multi-stacked device as claimed in claim 14 , wherein:
the in

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Pil-Kyu
• Lee Ho-Jin
• Park Byung-Lyul
• Kim Tae-Yeong
• Kim Seok-Ho

Classifications

• H02S40/30

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• Y02E10/50

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• F21S8/085 Primary

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