Interconnect apparatus and method

Patent metadata

Field	Value
Publication number	US-9536777-B2
Application number	US-201313890841-A
Country	US
Kind code	B2
Filing date	May 9, 2013
Priority date	Mar 13, 2013
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A method comprises bonding a first chip on a second chip, depositing a first hard mask layer over a non-bonding side of the first chip, depositing a second hard mask layer over the first hard mask layer, etching a first substrate of the first semiconductor chip using the second hard mask layer as a first etching mask and etching the IMD layers of the first chip and the second chip using the first hard mask layer as a second etching mask.

First claim

What is claimed is:

1. A method comprising:
bonding a first semiconductor chip on a second semiconductor chip, wherein:
the first semiconductor chip comprises a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first interconnect structures formed in the plurality of first inter-metal dielectric layers over the first substrate; and
the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second interconnect structures formed in the plurality of second inter-metal dielectric layers over the second substrate;

depositing a first hard mask layer over a non-bonding side of the first semiconductor chip;
depositing a second hard mask layer over the first hard mask layer;
patterning the first hard mask layer and the second hard mask layer to form a hard mask pattern;
after patterning the first hard mask layer and the second hard mask layer to form the hard mask pattern, etching the first substrate using the first hard mask layer and the second hard mask layer as a first mask;
removing the entire second hard mask layer;
etching the plurality of first inter-metal dielectric layers and the plurality of second inter-metal dielectric layers to form a plurality of openings, wherein the first hard mask layer is used as a second mask to form a first opening of the plurality of openings in an upper portion of the plurality of first inter-metal dielectric layers and the plurality of first interconnect structures are used as a third mask to form a second opening of the plurality of openings in a lower portion of the plurality of first inter-metal dielectric layers and an upper portion of the plurality of second inter-metal dielectric layers; and
plating a conductive material in the plurality of openings.

2. The method of claim 1 , further comprising:
plating the conductive material in the plurality of openings to form a conductive plug, wherein:
a first portion of the conductive plug is adjacent to a bonding side of the first semiconductor chip; and
a second portion of the conductive plug is adjacent to the non-bonding side of the first semiconductor chip, and wherein:
the second portion is of a width greater than or equal to a width of the first portion of the conductive plug.

3. The method of claim 1 , further comprising:
etching the plurality of first inter-metal dielectric layers and the plurality of second inter-metal dielectric layers to form the second opening of the plurality of openings, wherein the first hard mask layer and a plurality of first metal lines formed in the plurality of first inter-metal dielectric layer are used as the third mask.

4. The method of claim 1 , wherein:
the first hard mask layer is formed of polysilicon.

5. The method of claim 1 , wherein:
the second hard mask layer is formed of oxide.

6. A method comprising:
bonding a first semiconductor wafer on a second semiconductor wafer, wherein:
the first semiconductor wafer comprises a first substrate, first inter-metal dielectric layers and first interconnect structures formed in the first inter-metal dielectric layers and over the first substrate; and
the second semiconductor wafer comprises a second substrate, second inter-metal dielectric layers and second interconnect structures formed in the second inter-metal dielectric layers and over the second substrate;

depositing a polysilicon layer over a non-bonding side of the first semiconductor wafer;
depositing an oxide layer over the polysilicon layer;
patterning the polysilicon layer and the oxide layer to form a hard mask pattern;
after patterning the polysilicon layer and the oxide layer to form the hard mask pattern, forming a first opening in the first substrate using a first etching process and using the polysilicon layer and the oxide layer as a first mask layer;
removing the oxide layer prior to forming a second opening using a second etching process and using the polysilicon layer and the first interconnect structures as a second mask layer, wherein the second opening includes a first portion formed through the first inter-metal dielectric layers and a second portion formed partially through the second inter-metal dielectric layers, and wherein a width of the second portion is equal to a distance between two metal lines of the first inter-metal dielectric layers; and
plating a conductive material in the first opening and the second opening.

7. The method of claim 6 , further comprising:
depositing a bottom anti-reflection coating layer on a non-bonding side of the first semiconductor wafer, wherein the bottom anti-reflection coating layer is formed underneath the polysilicon layer.

8. The method of claim 6 , further comprising:
forming the second opening using the polysilicon layer and a plurality of metal lines of the first inter-metal dielectric layers as the second mask layer.

9. The method of claim 6 , wherein:
the conductive material is copper.

10. A method comprising:
bonding a first chip on a second chip, wherein:
the first chip comprises a first substrate portion and a first interconnect portion, and wherein the first interconnect portion comprises a plurality of first interconnect structures and a first inter-metal dielectric layer; and
the second chip comprises a second substrate portion and a second interconnect portion, and wherein the second interconnect portion comprises a plurality of second interconnect structures and a second inter-metal dielectric layer, and wherein a top surface of the first inter-metal dielectric layer of the first interconnect portion is in direct contact with a top surface of the second inter-metal dielectric layer of the second interconnect portion after performing the step of bonding the first chip on the second chip;

depositing a first hard mask layer over a non-bonding side of the first chip;
depositing a second hard mask layer over the first hard mask layer;
patterning the first hard mask layer and the second hard mask layer to form a hard mask pattern;
after patterning the first hard mask layer and the second hard mask layer to form the hard mask pattern, based upon the hard mask pattern, removing an exposed portion of the first substrate portion to form a first opening through a first etching process, wherein the second hard mask layer functions as a hard mask layer; and
forming a second opening through a second etching process, wherein the first hard mask layer, the plurality of first interconnect structures in the first interconnect portion and the plurality of second interconnect structures in the second interconnect portion function as hard mask layers after the second hard mask layer has been removed prior to the step of forming the second opening through the second etching process, and wherein a width of lower portion of the second opening is equal to a distance between two metal lines of the plurality of first interconnect structures.

11. The method of claim 10 , wherein:
the first hard mask layer is formed of polysilicon; and
the second hard mask layer is formed of oxide.

12. The method of claim 10 , wherein:
the second opening comprising a lower portion and an upper portion, and wherein:
the upper portion is in the first interconnect portion; and
the lower portion has a first portion in the first interconnect portion and a second portion in the second interconnect portion.

13. The method of claim 12 , wherein:
a width of the upper portion of the second opening is equal to a width of the first opening.

14. The method of claim 10 , further comprising:
depositing a dielectric layer alo

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Manufacutring Company Ltd

Inventors

• Lin Jeng-Shyan
• Tsai Shu-Ting
• Yaung Dun-Nian
• Liu Jen-Cheng
• Hung Feng-Chi
• Chou Shih Pei
• Kao Min-Feng
• Chen Szu-Ying

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title