Dynamic window to improve NAND endurance

Patent metadata

Field	Value
Publication number	US-9857992-B2
Application number	US-201615076963-A
Country	US
Kind code	B2
Filing date	Mar 22, 2016
Priority date	Dec 29, 2011
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
memory controller logic to apply a first trim profile to a flash memory storage device; and
the first trim profile to dynamically cause a program-erase window to vary by starting with an initial value and to modify the initial value with subsequent cycles over a life of the flash memory storage device based on a current cycle count value,
wherein the memory controller logic is to apply a second trim profile to the flash memory storage device in response to a determination that the current cycle count value has exceeded a threshold value or in response to occurrence of a failure condition, wherein the first trim profile or the second trim profile is to comprise one or more of: verify voltages, programming voltages, erase voltages, unselected WL (Word Line) read voltages, and erase or program pulse duration, wherein a smaller program-erase window is to be utilized during an initial life of the flash memory storage device.

2. The apparatus of claim 1 , wherein the occurrence of the failure condition is to be detected based on a ECC (Error Correcting Code) event.

3. The apparatus of claim 1 , wherein the occurrence of the failure condition is to be detected based on a Block Fail Rate (BFR) value.

4. The apparatus of claim 1 , further comprising a storage device or register to store the current cycle count value.

5. The apparatus of claim 1 , wherein the flash memory storage device is to comprise a NAND storage device.

6. The apparatus of claim 1 , wherein the program-erase window corresponds to a Multi Level Cell (MLC) window.

7. The apparatus of claim 1 , wherein one or more processor cores are coupled to the memory controller logic to access data stored in the flash memory storage device.

8. A method comprising:
applying a first trim profile to a flash memory storage device by memory controller logic, wherein the first trim profile dynamically causes a program-erase window to vary by starting with an initial value and modifying the initial value with subsequent cycles over a life of the flash memory storage device based on a current cycle count value;
applying a second trim profile to the flash memory storage device in response to a determination that the current cycle count value has exceeded a threshold value or in response to occurrence of a failure condition,
wherein the first trim profile or the second trim profile comprises one or more of: verify voltages, programming voltages, erase voltages, unselected WL (Word Line) read voltages, and erase or program pulse duration, wherein a smaller program-erase window is utilized during an initial life of the flash memory storage device.

9. The method of claim 8 , further comprising detecting the occurrence of the failure condition based on a ECC (Error Correcting Code) event.

10. The method of claim 8 , further comprising detecting the occurrence of the failure condition based on a Block Fail Rate (BFR) value.

11. One or more non-transitory computer-readable medium comprising one or more instructions that when executed on at least one a processor configure the at least one processor to perform one or more operations to:
apply a first trim profile to a flash memory storage device by memory controller logic, wherein the first trim profile dynamically causes a program-erase window to vary by starting with an initial value and modifying the initial value with subsequent cycles over a life of the flash memory storage device based on a current cycle count value;
apply a second trim profile to the flash memory storage device in response to a determination that the current cycle count value has exceeded a threshold value or in response to occurrence of a failure condition,
wherein the first trim profile or the second trim profile comprises one or more of: verify voltages, programming voltages, erase voltages, unselected WL (Word Line) read voltages, and erase or program pulse duration, wherein one or more instructions, when executed on the at least one processor, are to configure the at least one processor to perform one or more operations to cause utilization of a smaller program-erase window during an initial life of the flash memory storage device.

12. The one or more non-transitory computer-readable medium of claim 11 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause detection of the occurrence of the failure condition based on a ECC (Error Correcting Code) event.

13. The one or more non-transitory computer-readable medium of claim 11 , further comprising one or more instructions that when executed on the at least one processor configure the at least one processor to perform one or more operations to cause detection of the occurrence of the failure condition based on a Block Fail Rate (BFR) value.

14. A system comprising:
a NAND memory having a plurality of memory cells;
a processor to access the NAND memory; and
NAND memory controller logic to apply a first trim profile to the NAND memory, the first trim profile to dynamically cause a program-erase window to vary by starting with an initial value and modifying the initial value with subsequent cycles over a life of the NAND memory based on a current cycle count value,
wherein the NAND memory controller logic is to apply a second trim profile to the NAND memory in response to a determination that the current cycle count value has exceeded a threshold value or in response to occurrence of a failure condition
wherein the first trim profile or the second trim profile is to comprise one or more of: verify voltages, programming voltages, erase voltages, unselected WL (Word Line) read voltages, and erase or program pulse duration, wherein a smaller program-erase window is to be utilized during an initial life of the NAND memory.

15. The system of claim 14 , wherein the occurrence of the failure condition is to be detected based on a ECC (Error Correcting Code) event.

16. The system of claim 14 , wherein the occurrence of the failure condition is to be detected based on a Block Fail Rate (BFR) value.

Assignees

• Intel Corp

Inventors

• Pangal Kiran
• Kumar Ravi J

Classifications

• G11C16/00

  Erasable programmable read-only memories (G11C14/00 takes precedence) · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/2094

  Redundant storage or storage space (G06F11/2056 takes precedence) · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C16/3436

  Arrangements for verifying correct programming or erasure · CPC title