Adaptive and/or iterative operations in executing a read command to retrieve data from memory cells

Patent metadata

Field	Value
Publication number	US-11775217-B2
Application number	US-202117534850-A
Country	US
Kind code	B2
Filing date	Nov 24, 2021
Priority date	Mar 2, 2020
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

A memory sub-system configured to adaptively and/or iteratively determine sub-operations of executing a read command to retrieve data from memory cells. For example, after receiving the read command from a processing device of a memory sub-system, a memory device starts an atomic operation of executing the read command in the memory device. The memory device can have one or more groups of memory cells formed on an integrated circuit die and a calibration circuit configured to measure signal and noise characteristics of memory cells in the memory device. During the atomic operation, the calibration circuit generates outputs, based on which a read manager of the memory sub-system identifies sub-operations to be performed in the atomic operation and/or decides to end the atomic operation.

First claim

What is claimed is:

1. A device, comprising:
memory cells;
and
a logic circuit coupled to the memory cells and configured to, in response to a read command:
measure first signal and noise characteristics of the memory cells; and
determine, based on the first signal and noise characteristics, whether to measure second signal and noise characteristics of the memory cells.

2. The device of claim 1 , wherein the logic circuit is further configured to identify, based on the first signal and noise characteristics, a sub-operation to be performed for the read command.

3. The device of claim 1 , wherein the logic circuit is further configured to determine, iteratively, whether to measure further signal and noise characteristics of the memory cells based on a current measurement of signal and noise characteristics of the memory cells.

4. The device of claim 1 , wherein the logic circuit is further configured to:
calculate a first read voltage from the first signal and noise characteristics; and
determine, based on the first signal and noise characteristics, whether to read the memory cells at the first read voltage.

5. The device of claim 4 , wherein the logic circuit is further configured to:
determine, based on the first signal and noise characteristics, whether to read the memory cells at a second read voltage having a predetermined offset from the first read voltage.

6. The device of claim 1 , wherein the logic circuit is further configured to:
determine, based on the first signal and noise characteristics, a classification of an error rate of data retrievable from the group of memory cells using a first read voltage computed from the first signal and noise characteristics; and
determine, based on the classification, whether to read the memory cells at the first read voltage.

7. The device of claim 6 , wherein the logic circuit is further configured to:
determine, based on the classification, whether to read the memory cells at a second read voltage having a predetermined offset from the first read voltage.

8. The device of claim 1 , wherein the logic circuit is further configured to:
determine, based on the first signal and noise characteristics, whether to decode data retrieved from the memory cells using a first read voltage computed from the first signal and noise characteristics.

9. The device of claim 1 , further comprising:
an integrated circuit package configured to enclose the device, wherein the read command is received from outside of the integrated circuit package.

10. The device of claim 1 , wherein the first signal and noise characteristics of the memory cells includes, among the memory cells, a plurality of counts of first memory cells that have a predetermined status when a plurality of test voltages are applied respectively for the plurality of counts.

11. A method, comprising:
receiving, in a device having memory cells, a read command; and
in response to the read command:
measuring first signal and noise characteristics of the memory cells; and
determining, based on the first signal and noise characteristics, whether to measure second signal and noise characteristics of the memory cells.

12. The method of claim 11 , further comprising:
determining, iteratively, whether to measure further signal and noise characteristics of the memory cells based on a current measurement of signal and noise characteristics of the memory cells.

13. The method of claim 11 , further comprising:
determining, based on the first signal and noise characteristics, whether to perform a sub-operation for the read command.

14. The method of claim 13 , wherein the sub-operation includes:
reading the memory cells at a first read voltage computed from the first signal and noise characteristics;
reading the memory cells at a second read voltage having a predetermined offset from the first read voltage;
decoding data retrieved via reading the memory cells at the first read voltage;
decoding data retrieved via reading the memory cells at the first read voltage and reading the memory cells at the second read voltage; or
any combination thereof.

15. The method of claim 14 , further comprising:
determining, based on the first signal and noise characteristics, a classification of an error rate of data retrievable from the group of memory cells, wherein whether to perform the sub-operation is based on the classification.

16. The method of claim 15 , wherein device is enclosed within an integrated circuit package; and wherein the read command is received from outside of the integrated circuit package.

17. The method of claim 16 , wherein the first signal and noise characteristics of the memory cells includes, among the memory cells, a plurality of counts of first memory cells that have a predetermined status when a plurality of test voltages are applied respectively for the plurality of counts.

18. An apparatus, comprising:
a processing device configured to issue a read command; and
a memory device coupled to the processing device and enclosed in an integrated circuit package, the memory device having:
memory cells;
and
a logic circuit coupled to the memory cells and configured to, in response to the read command:
measure first signal and noise characteristics of the memory cells; and
determine, based on the first signal and noise characteristics, whether to measure second signal and noise characteristics of the memory cells.

19. The apparatus of claim 18 , wherein the memory device is configured to:
determine, based on the first signal and noise characteristics, a classification of an error rate of data retrievable from the group of memory cells; and
determine, based on the classification, whether to perform a sub-operation for the read command.

20. The apparatus of claim 19 , wherein the sub-operation includes:
reading the memory cells at a first read voltage computed from the first signal and noise characteristics;
reading the memory cells at a second read voltage having a predetermined offset from the first read voltage;
decoding data retrieved via reading the memory cells at the first read voltage;
decoding data retrieved via reading the memory cells at the first read voltage and reading the memory cells at the second read voltage; or
any combination thereof.

Assignees

• Micron Technology Inc

Inventors

• Fitzpatrick James
• Parthasarathy Sivagnanam
• Khayat Patrick Robert
• Alhussien Abdelhakim S

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title