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US-2024233829-A9 · Jul 11, 2024 · US
Solid state storage device and sensing voltage setting method thereof
US9129698B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9129698-B2 |
| Application number | US-201414160566-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 22, 2014 |
| Priority date | Nov 5, 2013 |
| Publication date | Sep 8, 2015 |
| Grant date | Sep 8, 2015 |
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Abstract
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A solid state storage device and sensing voltage setting method thereof are provided, and the method includes following steps. A predetermined read voltage of the memory cells is adjusted to obtain a plurality of detection read voltages. The predetermined read voltage and the detection read voltages are respectively applied to a plurality of memory cells in order to read a plurality of verification bit data. A plurality of statistical parametric values between the predetermined read voltage and the detection read voltages adjacent to each other is calculated and recorded according to the verification bit data corresponding to the predetermined read voltage and the detection read voltages. An optimized read voltage is obtained according to the statistical parametric values.
First claim
Opening claim text (preview).
What is claimed is: 1. A sensing voltage setting method of a solid state storage device, wherein the solid state storage device comprises a flash memory module configured for storing data, the flash memory module has a plurality of memory cells, each of the memory cells has a first storage state and a second storage state, and the sensing voltage setting method comprises: adjusting a predetermined read voltage of the memory cells to obtain a plurality of detection read voltages;…
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Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G11C16/34Primary
Physics · mapped topic
Physics · mapped topic
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- What does patent US9129698B2 cover?
- A solid state storage device and sensing voltage setting method thereof are provided, and the method includes following steps. A predetermined read voltage of the memory cells is adjusted to obtain a plurality of detection read voltages. The predetermined read voltage and the detection read voltages are respectively applied to a plurality of memory cells in order to read a plurality of verifica…
- Who is the assignee on this patent?
- Lite On It Corp, Lite On Technology Corp
- What technology area does this patent fall under?
- Primary CPC classification G11C16/34. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Sep 08 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).