Cell current based bit line voltage

Patent metadata

Field	Value
Publication number	US-10008273-B2
Application number	US-201615181346-A
Country	US
Kind code	B2
Filing date	Jun 13, 2016
Priority date	Jun 13, 2016
Publication date	Jun 26, 2018
Grant date	Jun 26, 2018

Abstract

Apparatuses, systems, methods, and computer program products are disclosed for read level determination. A block of non-volatile storage cells has a plurality of bit lines. A controller for a block is configured to perform a first read on a set of storage cells using a first read level for the bit lines. A controller is configured to determine a second read level for at least a portion of the bit lines based at least partially on a first read. A controller is configured to perform a second read on a set of storage cells using a second read level for at least a portion of bit lines.

First claim

What is claimed is:

1. An apparatus comprising:
a block of non-volatile storage cells comprising a plurality of bit lines; and
a controller for the block, the controller configured to:
perform a first read on a set of storage cells using a first read level for the bit lines;
determine a second read level for at least a portion of the bit lines based at least partially on cell currents detected during the first read; and
perform a second read on the set of storage cells using the second read level for at least a portion of the bit lines.

2. The apparatus of claim 1 , wherein the controller is configured to:
determine which storage cells of the set of storage cells have cell currents on the bit lines that fail to satisfy a sensing threshold during the first read; and
use the second read level for bit lines of the determined storage cells during the second read.

3. The apparatus of claim 2 , wherein the second read level is greater than the first read level such that the cell currents for at least a portion of the determined storage cells increases during the second read.

4. The apparatus of claim 1 , wherein the controller comprises an error correcting code (ECC) decoder configured to use data from the first read to correct one or more data errors in data from the second read.

5. The apparatus of claim 1 , wherein hardware of a non-volatile storage device comprises the block of non-volatile storage cells and the controller.

6. The apparatus of claim 5 , wherein the hardware of the non-volatile storage device comprises a storage controller in communication with a plurality of semiconductor chips of non-volatile storage, one of the semiconductor chips comprising the block of non-volatile storage cells.

7. The apparatus of claim 5 , wherein the hardware of the non-volatile storage device comprises a state machine on the same semiconductor chip as the block of non-volatile storage cells.

8. The apparatus of claim 1 , wherein the controller comprises a device driver for a non-volatile storage device comprising the block of non-volatile storage cells, the device driver comprising a non-transitory computer readable storage medium storing executable code of the controller.

9. A method comprising:
performing a dummy read on a memory cell;
determining a bit line input for a bit line of the memory cell based at least partially on cell currents detected during the dummy read; and
performing a read on the memory cell using the determined bit line input.

10. The method of claim 9 , wherein multiple dummy reads are performed on a plurality of word lines comprising a plurality of memory cells, determining the bit line input comprises determining bit line inputs for a plurality of bit lines corresponding to the plurality of word lines, and performing the read of the memory cell comprises performing a read on one of the word lines corresponding to the memory cell using the different determined bit line inputs for the plurality of bit lines.

11. The method of claim 10 , wherein determining the bit line inputs for the plurality of bit lines comprises:
determining a number of failed memory cells for each bit line of the plurality of word lines based on the multiple dummy reads;
determining whether the number of failed memory cells for each bit line exceeds a predetermined threshold; and
using the determined bit line input during the read for bit lines where the number of failed memory cells for the bit line exceeds the predetermined threshold.

12. The method of claim 11 , further comprising:
selecting a first bit line input for bit lines of the plurality of bit lines with a number of failed memory cells that do not exceed the predetermined threshold; and
selecting a second bit line input for bit lines of the plurality of bit lines with a number of failed memory cells that do exceed the predetermined threshold.

13. The method of claim 12 , wherein the first bit line input comprises a bit line input used during the dummy read.

14. The method of claim 9 , wherein the dummy read is performed during a manufacturing and testing process for the memory cell.

15. The method of claim 9 , wherein the determined bit line input for the bit line is stored in a non-volatile memory medium comprising the memory cell.

16. The method of claim 9 , wherein performing the dummy read on the memory cell comprises performing the dummy read using a first bit line input and performing the read on the memory cell comprises performing the read using a second bit line input.

17. The method of claim 16 , wherein the first bit line input is less than the second bit line input in response to a cell current for the memory cell during the dummy read failing to satisfy a sensing threshold.

18. The method of claim 9 , wherein the dummy read is performed before the read of the memory cell.

19. An apparatus comprising:
means for performing a first read on cells of a non-volatile memory medium to determine cell currents used to read the cells;
means for determining bit line voltages for a plurality of bit lines corresponding to the cells based on the determined cell currents; and
means for performing a second read on the cells using the determined bit line voltages for the plurality of bit lines.

20. The apparatus of claim 19 , wherein the means for determining the bit line voltages selects a first bit line voltage for bit lines of the plurality of bit lines with cell currents that do not satisfy a predetermined threshold and selects a second bit line voltage for bit lines of the plurality of bit lines with cell currents that satisfy the predetermined threshold, wherein the second bit line voltage is greater than the first bit line voltage.

Assignees

• Sandisk Technologies Llc

Inventors

• Ray Biswajit
• Hemink Gerrit Jan
• Dunga Mohan
• Rajamohanan Bijesh
• Chen Changyuan

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C2029/1204

  Bit line control · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title