Peak current management in non-volatile storage

Patent metadata

Field	Value
Publication number	US-9947401-B1
Application number	US-201615388154-A
Country	US
Kind code	B1
Filing date	Dec 22, 2016
Priority date	Dec 22, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

Technology is described for keeping current (e.g., peak power supply current or ICC) in a non-volatile memory system within a target while maintaining high throughput. Programming conditions are adaptively changed at the sub-codeword level in order to keep power supply current of the memory system within a target. In one embodiment, a chunk of data that corresponds to a sub-codeword is written while consuming lower than normal programming current in order to keep power supply current within a target. The relatively low programming current may increase the expected raw BER. However, other portions of the codeword can be written with a higher than normal programming current, which results in a lower expected bit raw error rate for the memory cells that store that portion.

First claim

What is claimed is:

1. A non-volatile memory system, comprising:
a plurality of non-volatile memory cells;
a control circuit in communication with the plurality of non-volatile memory cells, the control circuit configured to:
monitor current consumption of the non-volatile memory system;
program data into the plurality of non-volatile memory cells in sub-codeword chunks; and
adjust programming conditions of the sub-codeword chunks in a selected codeword to keep the current consumption of the non-volatile memory system below a threshold current and an expected bit error rate (BER) of the selected codeword within a threshold BER, including the control circuit configured to limit a programming current used to program a first sub-codeword chunk into a set of the non-volatile memory cells to a current level expected to result in a BER for the first sub-codeword chunk that is greater than the threshold BER.

2. The non-volatile memory system of claim 1 , wherein the plurality of non-volatile memory cells are reversible resistivity memory cells.

3. The non-volatile memory system of claim 1 wherein, to adjust programming conditions of the sub-codeword chunks, the control circuit is configured to:
determine the BER that is expected to result if the set of non-volatile memory cells that are to store the first sub-codeword are programmed within a current budget;
determine a cumulative BER for the selected codeword based on the expected BER for the first sub-codeword chunk and expected BERs for other sub-codeword chunks of the selected codeword; and
program the set of non-volatile memory cells within the current budget responsive to a determination that the cumulative BER is less than the threshold BER.

4. The non-volatile memory system of claim 3 , wherein the expected BER for the first sub-codeword chunk is a first expected bit error rate, wherein the control circuit is further configured to:
program a second sub-codeword chunk of the selected codeword into non-volatile memory cells using a current that corresponds to a second expected BER that is lower than the first expected BER to stay within the threshold BER for the selected codeword.

5. The non-volatile memory system of claim 3 , wherein the control circuit is further configured to:
determine a log-likelihood ratio that will allow the selected codeword to be successfully decoded given the cumulative BER;
store the log-likelihood ratio; and
use the log-likelihood ratio to successfully decode the selected codeword.

6. The non-volatile memory system of claim 5 , wherein the threshold BER is a first threshold BER, wherein control circuit is further configured to:
mark the selected codeword as a candidate for a scrub operation responsive to a determination that the cumulative BER is less than the first threshold BER but more than a second threshold BER.

7. The non-volatile memory system of claim 3 , wherein the control circuit is further configured to:
mark the set of non-volatile memory cells as a candidate for a scrub operation responsive to a determination that the expected BER for the set of non-volatile memory cells is more than an allowed threshold for the set of non-volatile memory cells.

8. The non-volatile memory system of claim 1 , further comprising:
a plurality of memory dies, each die comprising a portion of the plurality of non-volatile memory cells, wherein the control circuit is further configured to:
monitor power supply current consumption of the plurality of memory dies; and
adjust the programming conditions of the sub-codeword chunks to keep the current consumption of the plurality of memory dies within an allowed peak power supply current responsive to a determination that the power supply current consumption of the plurality of memory dies is within a certain amount of the allowed peak power supply current.

9. The non-volatile memory system of claim 1 , wherein the plurality of non-volatile memory cells reside in a three-dimensional memory array.

10. A method of operating a non-volatile memory system, comprising:
accessing a total power supply current usage of a plurality of memory dies in the non-volatile memory system, each of the memory dies comprising reversible resistivity non-volatile memory cells;
programming data into reversible resistivity non-volatile memory cells in sub-codeword chunks;
adjusting programming conditions of the sub-codeword chunks in a selected codeword to keep the total power supply current usage below a threshold current and an expected bit error rate (BER) of the selected codeword within a decodable BER; and
limiting programming current when programming data into the reversible resistivity non-volatile memory cells in a first sub-codeword chunk of the selected codeword to keep the total power supply current within the threshold current despite the first sub-codeword chunk having an expected BER that is greater than the decodable BER for the selected codeword.

11. The method of claim 10 , wherein the adjusting programming conditions comprises:
predicting a bit error rate (BER) for programming the first sub-codeword chunk using a current budget that keeps the total power supply current from exceeding the threshold current;
predicting a cumulative BER for the selected codeword based on the predicted BER for the non-volatile memory cells that are to store the first sub-codeword chunk and predicted BERs for programming other sub-codeword chunks of the selected codeword; and
programming the non-volatile memory cells that are to store the first sub-codeword chunk within the current budget responsive to a determination that the predicted cumulative BER for the selected codeword is less than a BER that can be successfully decoded by a decoder in the memory system.

12. The method of claim 11 , further comprising:
determining a log-likelihood ratio that will allow the selected codeword to be successfully decoded by the decoder given the predicted cumulative BER for the selected codeword;
storing the log-likelihood ratio;
reading the selected codeword from reversible resistivity non-volatile memory cells; and
using the log-likelihood ratio to successfully decode the selected codeword.

13. The method of claim 11 , further comprising:
marking non-volatile memory cells that store the selected codeword as a candidate for a scrub operation responsive to a determination that the predicted cumulative BER of the selected codeword is less than a BER that can be successfully decoded by the decoder but more than a second BER that is less than the BER that can be successfully decoded by the decoder.

14. The method of claim 11 , wherein the predicting a bit error rate (BER) for programming the first sub-codeword chunk comprises:
factoring in a condition of the non-volatile memory cells that are to store the first sub-codeword chunk.

15. The method of claim 10 , wherein the limiting programming current comprises:
limiting a maximum programming current by applying a control voltage to a transistor.

16. The method of claim 10 , wherein the limiting programming current comprises:
limiting a programming current by applying a first select voltage to a selected word line and a second select voltage to a selected bit line.

17. A non-volatile memory system, comprising:
a plurality of memory dies, each memory die comprising a plurality of non-volatile reversible resistivity memory cells;
means for determining a power supply current usage for each of plurality of memory dies in the non-volatile memory system;
means for determining whether a total power supply current us

Assignees

• Sandisk Technologies Llc

Inventors

• Navon Ariel
• Liu Tz-Yi
• Sharon Eran
• Bazarsky Alexander
• Hahn Judah
• Eyal Alon
• Fainzilber Omer

Classifications

• G06F11/3034

  where the computing system component is a storage system, e.g. DASD based or network based (digital input from or digital output to record carriers G06F3/06; digital recording or reproducing G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/3062

  where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/0727

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title