Memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11770938-B2
Application number	US-202217592087-A
Country	US
Kind code	B2
Filing date	Feb 3, 2022
Priority date	Feb 22, 2016
Publication date	Sep 26, 2023
Grant date	Sep 26, 2023

Abstract

A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a driving circuit area disposed on the substrate;
a plurality of word lines extending in a first direction disposed on the driving circuit area, and including a first word line and a second word line spaced in parallel apart from each other in a second direction perpendicular to the first direction;
a plurality of bit lines extending in the second direction disposed on the word lines, and including a first bit line and a second bit line spaced in parallel apart from each other in the first direction;
a memory cell array area including a plurality of memory pillars respectively arranged at cross points between the plurality of bit lines and the plurality of first word lines, each of the plurality of memory pillars including a selection device and a variable resistance layer;
a plurality of insulating patterns disposed between two adjacent memory pillars among the plurality of memory pillars; and
a first capping layer disposed on a sloped side wall of each of the variable resistance layers,
wherein a width of the variable resistance layer gradually decreases in a direction from an upper portion to a middle portion and gradually increases in a direction from the middle portion to a lower portion.

2. The semiconductor device of claim 1 , further comprising:
a second capping layer disposed on a sloped side wall of each of the selection devices.

3. The semiconductor device of claim 2 ,
wherein a maximum thickness of the first capping layer is greater than a maximum thickness of the second capping layer.

4. The semiconductor device of claim 2 ,
wherein the second capping layer is spaced apart from the first capping layer.

5. The semiconductor device of claim 1 ,
wherein a width of the first capping layer increases in a direction from an upper portion to a middle portion and gradually decreases in a direction from the middle portion to a lower portion.

6. The semiconductor device of claim 1 , further comprising:
a top electrode disposed on the variable resistance layer,
wherein the sloped side wall of the variable resistance layer is disposed under the top electrode.

7. The semiconductor device of claim 1 ,
wherein the first capping layer surrounds substantially an entire portion of the sloped side wall of the variable resistance layer.

8. The semiconductor device of claim 1 , further comprising:
a plurality of transistors on the substrate,
wherein the driving circuit area includes a multilayer wiring structure electrically connected to the plurality of transistors.

9. The semiconductor device of claim 1 , further comprising:
a plurality of transistors on the substrate,
wherein the memory cell array area is connected to the plurality of transistors through a multilayer wiring structure.

10. The semiconductor device of claim 1 , further comprising:
a top insulating interlayer disposed on the driving circuit area; and
a wiring structure passing through the top insulating interlayer and connecting the memory cell array area and the driving circuit area.

11. The semiconductor device of claim 1 , further comprising:
an air spacer disposed in at least one of the plurality of insulating patterns.

12. A semiconductor device comprising:
a substrate;
a driving circuit area disposed on the substrate;
a plurality of word lines extending in a first direction disposed on the driving circuit area, and including a first word line and a second word line spaced in parallel apart from each other in a second direction perpendicular to the first direction;
a plurality of bit lines extending in the second direction disposed on the word lines, and including a first bit line and a second bit line spaced in parallel apart from each other in the first direction;
a memory cell array area including a plurality of memory pillars respectively arranged at cross points between the plurality of bit lines and the plurality of first word lines, each of the plurality of memory pillars including a selection device and a variable resistance layer;
a plurality of insulating patterns disposed between two adjacent memory pillars among the plurality of memory pillars; and
a first capping layer disposed in a recessed portion of each of the variable resistance layers,
wherein the recessed portion has a first sloped profile directing toward an inner side from an upper portion to a middle portion and a second sloped profile directing toward an outer side from the middle portion to a lower portion.

13. The semiconductor device of claim 12 , further comprising:
a second capping layer disposed on a side wall of each of the selection devices.

14. The semiconductor device of claim 13 ,
wherein a maximum thickness of the first capping layer is greater than a maximum thickness of the second capping layer.

15. The semiconductor device of claim 13 ,
wherein the second capping layer is spaced apart from the first capping layer.

16. The semiconductor device of claim 12 ,
wherein a width of the first capping layer in the recessed portion increases in a direction from an upper portion to a middle portion and gradually decreases in a direction from the middle portion to a lower portion.

17. The semiconductor device of claim 12 , further comprising:
a top electrode disposed on the variable resistance layer,
wherein a side wall of the recessed portion of the variable resistance layer is disposed under the top electrode.

18. The semiconductor device of claim 12 ,
wherein the first capping layer surrounds substantially an entire portion of a side wall of the variable resistance layer.

19. The semiconductor device of claim 12 , further comprising:
a plurality of transistors on the substrate,
wherein the driving circuit area includes a multilayer wiring structure electrically connected to the plurality of transistors.

20. The semiconductor device of claim 12 , further comprising:
a plurality of transistors on the substrate,
wherein the memory cell array area is connected to the plurality of transistors through a multilayer wiring structure.

21. The semiconductor device of claim 12 , further comprising:
a top insulating interlayer disposed on the driving circuit area; and
a wiring structure passing through the top insulating interlayer and connecting the memory cell array area and the driving circuit area.

22. The semiconductor device of claim 12 , further comprising:
an air spacer disposed in at least one of the plurality of insulating patterns.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seong Dong-Jun
• Park Soon-Oh

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10B63/24 Primary

  of the Ovonic threshold switching type · CPC title

• H10B63/84 Primary

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H10B63/845

  the switching components being connected to a common vertical conductor · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title